ZHCSHA1 November   2019 ADS8686S

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      器件框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Specifications: Universal
    9. 6.9  Timing Requirements: Parallel Data Read
    10. 6.10 Timing Requirements: Serial Data Read
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Programmable, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer
      8. 7.3.8  Digital Filter and Noise
      9. 7.3.9  Reference
        1. 7.3.9.1 Internal Reference
        2. 7.3.9.2 External Reference
        3. 7.3.9.3 Supplying One VREF to Multiple Devices
      10. 7.3.10 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RESET (Input)
        3. 7.4.1.3  SEQEN (Input)
        4. 7.4.1.4  HW_RANGESEL[1:0] (Input)
        5. 7.4.1.5  SER/BYTE/PAR (Input)
        6. 7.4.1.6  DB[3:0] (Input/Output)
        7. 7.4.1.7  DB4/SER1W (Input/Output)
        8. 7.4.1.8  DB5/CRCEN (Input/Output)
        9. 7.4.1.9  DB[7:6] (Input/Output)
        10. 7.4.1.10 DB8 (Input/Output)
        11. 7.4.1.11 DB9/BYTESEL (Input/Output)
        12. 7.4.1.12 DB10/SDI (Input/Output)
        13. 7.4.1.13 DB11/SDOB (Input/Output)
        14. 7.4.1.14 DB12/SDOA (Input/Output)
        15. 7.4.1.15 DB13/OS0 (Input/Output)
        16. 7.4.1.16 DB14/OS1 (Input/Output)
        17. 7.4.1.17 DB15/OS2 (Input/Output)
        18. 7.4.1.18 WR/BURST (Input)
        19. 7.4.1.19 SCLK/RD (Input)
        20. 7.4.1.20 CS (Input)
        21. 7.4.1.21 CHSEL[2:0] (Input)
        22. 7.4.1.22 BUSY (Output)
        23. 7.4.1.23 CONVST (Input)
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Shutdown Mode
        2. 7.4.2.2 Operation Mode
          1. 7.4.2.2.1 Hardware Mode
          2. 7.4.2.2.2 Software Mode
        3. 7.4.2.3 Reset Functionality
        4. 7.4.2.4 Channel Selection
          1. 7.4.2.4.1 Hardware Mode Channel Selection
          2. 7.4.2.4.2 Software Mode Channel Selection
        5. 7.4.2.5 Sequencer
          1. 7.4.2.5.1 Hardware Mode Sequencer
          2. 7.4.2.5.2 Software Mode Sequencer
        6. 7.4.2.6 Burst Sequencer
          1. 7.4.2.6.1 Hardware Mode Burst Sequencer
          2. 7.4.2.6.2 Software Mode Burst Sequencer
        7. 7.4.2.7 Diagnostics
          1. 7.4.2.7.1 Analog Diagnosis
          2. 7.4.2.7.2 Interface Diagnosis: SELF TEST and CRC
    5. 7.5 Programming
      1. 7.5.1 Parallel Interface
        1. 7.5.1.1 Reading Conversion Results
        2. 7.5.1.2 Writing Register Data
        3. 7.5.1.3 Reading Register Data
      2. 7.5.2 Parallel Byte Interface
        1. 7.5.2.1 Reading Conversion Results
        2. 7.5.2.2 Writing Register Data
        3. 7.5.2.3 Reading Register Data
      3. 7.5.3 Serial Interface
        1. 7.5.3.1 Reading Conversion Results
        2. 7.5.3.2 Writing Register Data
        3. 7.5.3.3 Reading Register Data
    6. 7.6 Register Maps
      1. 7.6.1 Page1 Registers
        1. 7.6.1.1  CONFIGURATION Register (Address = 0x2) [reset = 0x400]
          1. Table 15. CONFIGURATION Register Field Descriptions
        2. 7.6.1.2  CHANNEL_SEL Register (Address = 0x3) [reset = 0x600]
          1. Table 16. CHANNEL_SEL Register Field Descriptions
        3. 7.6.1.3  RANGE_A1 Register (Address = 0x4) [reset = 0x8FF]
          1. Table 17. RANGE_A1 Register Field Descriptions
        4. 7.6.1.4  RANGE_A2 Register (Address = 0x5) [reset = 0xAFF]
          1. Table 18. RANGE_A2 Register Field Descriptions
        5. 7.6.1.5  RANGE_B1 Register (Address = 0x6) [reset = 0xCFF]
          1. Table 19. RANGE_B1 Register Field Descriptions
        6. 7.6.1.6  RANGE_B2 Register (Address = 0x7) [reset = 0xEFF]
          1. Table 20. RANGE_B2 Register Field Descriptions
        7. 7.6.1.7  STATUS Register (Address = 0x8) [reset = 0x0]
          1. Table 21. STATUS Register Field Descriptions
        8. 7.6.1.8  OVER_RANGE_SETTING_A Register (Address = 0xA) [reset = 0x1400]
          1. Table 22. OVER_RANGE_SETTING_A Register Field Descriptions
        9. 7.6.1.9  OVER_RANGE_SETTING_B Register (Address = 0xB) [reset = 0x1600]
          1. Table 23. OVER_RANGE_SETTING_B Register Field Descriptions
        10. 7.6.1.10 LPF_CONFIG Register (Address = 0xD) [reset = 0x1A00]
          1. Table 24. LPF_CONFIG Register Field Descriptions
        11. 7.6.1.11 Device_ID Register (Address = 0x10) [reset = 0x2002]
          1. Table 25. Device_ID Register Field Descriptions
        12. 7.6.1.12 SEQ_STACK_0 Register (Address = 0x20) [reset = 0x4000]
          1. Table 26. SEQ_STACK_0 Register Field Descriptions
        13. 7.6.1.13 SEQ_STACK_1 Register (Address = 0x21) [reset = 0x4211]
          1. Table 27. SEQ_STACK_1 Register Field Descriptions
        14. 7.6.1.14 SEQ_STACK_2 Register (Address = 0x22) [reset = 0x4422]
          1. Table 28. SEQ_STACK_2 Register Field Descriptions
        15. 7.6.1.15 SEQ_STACK_3 Register (Address = 0x23) [reset = 0x4633]
          1. Table 29. SEQ_STACK_3 Register Field Descriptions
        16. 7.6.1.16 SEQ_STACK_4 Register (Address = 0x24) [reset = 0x4844]
          1. Table 30. SEQ_STACK_4 Register Field Descriptions
        17. 7.6.1.17 SEQ_STACK_5 Register (Address = 0x25) [reset = 0x4A55]
          1. Table 31. SEQ_STACK_5 Register Field Descriptions
        18. 7.6.1.18 SEQ_STACK_6 Register (Address = 0x26) [reset = 0x4C66]
          1. Table 32. SEQ_STACK_6 Register Field Descriptions
        19. 7.6.1.19 SEQ_STACK_7 Register (Address = 0x27) [reset = 0x4F77]
          1. Table 33. SEQ_STACK_7 Register Field Descriptions
        20. 7.6.1.20 SEQ_STACK_8 Register (Address = 0x28) [reset = 0x5000]
          1. Table 34. SEQ_STACK_8 Register Field Descriptions
        21. 7.6.1.21 SEQ_STACK_9 Register (Address = 0x29) [reset = 0x5200]
          1. Table 35. SEQ_STACK_9 Register Field Descriptions
        22. 7.6.1.22 SEQ_STACK_10 Register (Address = 0x2A) [reset = 0x5400]
          1. Table 36. SEQ_STACK_10 Register Field Descriptions
        23. 7.6.1.23 SEQ_STACK_11 Register (Address = 0x2B) [reset = 0x5600]
          1. Table 37. SEQ_STACK_11 Register Field Descriptions
        24. 7.6.1.24 SEQ_STACK_12 Register (Address = 0x2C) [reset = 0x5800]
          1. Table 38. SEQ_STACK_12 Register Field Descriptions
        25. 7.6.1.25 SEQ_STACK_13 Register (Address = 0x2D) [reset = 0x5A00]
          1. Table 39. SEQ_STACK_13 Register Field Descriptions
        26. 7.6.1.26 SEQ_STACK_14 Register (Address = 0x2E) [reset = 0x5C00]
          1. Table 40. SEQ_STACK_14 Register Field Descriptions
        27. 7.6.1.27 SEQ_STACK_15 Register (Address = 0x2F) [reset = 0x5E00]
          1. Table 41. SEQ_STACK_15 Register Field Descriptions
        28. 7.6.1.28 SEQ_STACK_16 Register (Address = 0x30) [reset = 0x6000]
          1. Table 42. SEQ_STACK_16 Register Field Descriptions
        29. 7.6.1.29 SEQ_STACK_17 Register (Address = 0x31) [reset = 0x6200]
          1. Table 43. SEQ_STACK_17 Register Field Descriptions
        30. 7.6.1.30 SEQ_STACK_18 Register (Address = 0x32) [reset = 0x6400]
          1. Table 44. SEQ_STACK_18 Register Field Descriptions
        31. 7.6.1.31 SEQ_STACK_19 Register (Address = 0x33) [reset = 0x6600]
          1. Table 45. SEQ_STACK_19 Register Field Descriptions
        32. 7.6.1.32 SEQ_STACK_20 Register (Address = 0x34) [reset = 0x6800]
          1. Table 46. SEQ_STACK_20 Register Field Descriptions
        33. 7.6.1.33 SEQ_STACK_21 Register (Address = 0x35) [reset = 0x6A00]
          1. Table 47. SEQ_STACK_21 Register Field Descriptions
        34. 7.6.1.34 SEQ_STACK_22 Register (Address = 0x36) [reset = 0x6C00]
          1. Table 48. SEQ_STACK_22 Register Field Descriptions
        35. 7.6.1.35 SEQ_STACK_23 Register (Address = 0x37) [reset = 0x6E00]
          1. Table 49. SEQ_STACK_23 Register Field Descriptions
        36. 7.6.1.36 SEQ_STACK_24 Register (Address = 0x38) [reset = 0x7000]
          1. Table 50. SEQ_STACK_24 Register Field Descriptions
        37. 7.6.1.37 SEQ_STACK_25 Register (Address = 0x39) [reset = 0x7200]
          1. Table 51. SEQ_STACK_25 Register Field Descriptions
        38. 7.6.1.38 SEQ_STACK_26 Register (Address = 0x3A) [reset = 0x7400]
          1. Table 52. SEQ_STACK_26 Register Field Descriptions
        39. 7.6.1.39 SEQ_STACK_27 Register (Address = 0x3B) [reset = 0x7600]
          1. Table 53. SEQ_STACK_27 Register Field Descriptions
        40. 7.6.1.40 SEQ_STACK_28 Register (Address = 0x3C) [reset = 0x7800]
          1. Table 54. SEQ_STACK_28 Register Field Descriptions
        41. 7.6.1.41 SEQ_STACK_29 Register (Address = 0x3D) [reset = 0x7A00]
          1. Table 55. SEQ_STACK_29 Register Field Descriptions
        42. 7.6.1.42 SEQ_STACK_30 Register (Address = 0x3E) [reset = 0x7C00]
          1. Table 56. SEQ_STACK_30 Register Field Descriptions
        43. 7.6.1.43 SEQ_STACK_31 Register (Address = 0x3F) [reset = 0x7E00]
          1. Table 57. SEQ_STACK_31 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 8x2 Channel Data Acquisition System (DAQ) for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Input Protection for Electrical Overstress
  9. Power Supply Recommendations
    1. 9.1 Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

特性

  • 16 通道、16 位 ADC,具有集成模拟前端
  • 双路同步采样:8x2 个通道
  • 电源:
    • 模拟:5V
    • 数字:1.8V 至 5V
  • 恒定 1MΩ 输入阻抗前端
  • 可独立编程的输入范围,具有 20% 的超范围
  • 可编程低通滤波器
  • 出色的直流和交流性能
  • 片上基准和基准缓冲器
  • 出色的过热保护性能
  • 8kV ESD 过压输入钳位
  • 可选的循环冗余校验 (CRC) 错误检查
  • 片上自诊断功能
  • 温度范围:–40°C 至 +125°C