ZHCSD79A January   2015  – August 2019 ADS54J54

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: 250 MSPS Output, 2x Decimation Filter
    7. 6.7  Electrical Characteristics: 500 MSPS Output
    8. 6.8  Electrical Characteristics: Sample Clock Timing Characteristics
    9. 6.9  Electrical Characteristics: Digital Outputs
    10. 6.10 Timing Requirements
    11. 6.11 Reset Timing
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Decimation by 2 (250 MSPS Output)
      2. 7.3.2  Over-Range Indication
      3. 7.3.3  JESD204B Interface
        1. 7.3.3.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.3.3.2 JESD204B Test Patterns
        3. 7.3.3.3 JESD204B Frame Assembly
      4. 7.3.4  SYSREF Clocking Schemes
      5. 7.3.5  Split-Mode Operation
      6. 7.3.6  Eye Diagram Information
      7. 7.3.7  Analog Inputs
      8. 7.3.8  Clock Inputs
      9. 7.3.9  Input Clock Divider
      10. 7.3.10 Power-Down Control
      11. 7.3.11 Device Configuration
      12. 7.3.12 JESD204B Interface Initialization Sequence
      13. 7.3.13 Device and Register Initialization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Output Format
    5. 7.5 Programming
      1. 7.5.1 Serial Register Write
      2. 7.5.2 Serial Register Readout
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  Register Address 0
          1. Table 9. Register Address 0 Field Descriptions
        2. 7.6.1.2  Register Address 1
          1. Table 10. Register Address 1 Field Descriptions
        3. 7.6.1.3  Register Address 3
          1. Table 11. Register Address 3 Field Descriptions
        4. 7.6.1.4  Register Address 4
          1. Table 12. Register Address 4 Field Descriptions
        5. 7.6.1.5  Register Address 5
          1. Table 13. Register Address 5 Field Descriptions
          2. Table 14. Configurations When ENABLE Pin is Low
        6. 7.6.1.6  Register Address 6
          1. Table 15. Register Address 6 Field Descriptions
          2. Table 16. Configurations When ENABLE Pin is High
        7. 7.6.1.7  Register Address 7
          1. Table 17. Register Address 7 Field Descriptions
        8. 7.6.1.8  Register Address 8
          1. Table 18. Register Address 8 Field Descriptions
        9. 7.6.1.9  Register Address 12
          1. Table 19. Register Address 12 Field Descriptions
        10. 7.6.1.10 Register Address 13
          1. Table 20. Register Address 13 Field Descriptions
        11. 7.6.1.11 Register Address 14
          1. Table 21. Register Address 14 Field Descriptions
        12. 7.6.1.12 Register Address 15
          1. Table 22. Register Address 15 Field Descriptions
        13. 7.6.1.13 Register Address 16
          1. Table 23. Register Address 16 Field Descriptions
        14. 7.6.1.14 Register Address 19
          1. Table 24. Register Address 19 Field Descriptions
        15. 7.6.1.15 Register Address 22
          1. Table 25. Register Address 22 Field Descriptions
        16. 7.6.1.16 Register Address 23
          1. Table 26. Register Address 23 Field Descriptions
        17. 7.6.1.17 Register Address 26
          1. Table 27. Register Address 26 Field Descriptions
        18. 7.6.1.18 Register Address 29
          1. Table 28. Register Address 29 Field Descriptions
        19. 7.6.1.19 Register Address 30
          1. Table 29. Register Address 30 Field Descriptions
          2. Table 30. Configurations
        20. 7.6.1.20 Register Address 31
          1. Table 31. Register Address 31 Field Descriptions
          2. Table 32. Configurations
        21. 7.6.1.21 Register Address 32
          1. Table 33. Register Address 32 Field Descriptions
        22. 7.6.1.22 Register Address 33
          1. Table 34. Register Address 33 Field Descriptions
        23. 7.6.1.23 Register Address 99
          1. Table 35. Register Address 99 Field Descriptions
        24. 7.6.1.24 Register Address 100
          1. Table 36. Register Address 100 Field Descriptions
        25. 7.6.1.25 Register Address 103
          1. Table 37. Register Address 103 Field Descriptions
          2. Table 38. Pre-Emphasis Level is: Decimal Value / 30
        26. 7.6.1.26 Register Address 104
          1. Table 39. Register Address 104 Field Descriptions
        27. 7.6.1.27 Register Address 107
          1. Table 40. Register Address 107 Field Descriptions
          2. Table 41. Pre-Emphasis Level is: Decimal Value / 30
        28. 7.6.1.28 Register Address 108
          1. Table 42. Register Address 108 Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
    4. 8.4 Detailed Design Procedure
      1. 8.4.1 SNR and Clock Jitter
    5. 8.5 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML SerDes Transmitter Interface
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 Register Maps

Register Address Register Data
A7 to A0 in hex D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 3/4 WIRE FORMAT DEC EN AB HP/LP AB 0 DEC EN CD HP/LP CD 0 0 0 0 0 0 0 0 RESET
1 MODE 1 0 1 0 FOVR THRESH AB FOVR LENGTH AB FOVR THRESH CD FOVR LENGTH CD 1 0
2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
3 0 CLK SEL CD CLK DIV CD 0 CLK PHASE SELECT CD SYSREF SEL CD CLK SEL AB CLK DIV AB 0 CLK PHASE SELECT AB
4 OVRA OUT EN OVRB OUT EN OVRC OUT EN OVRD OUT EN SYSREF AB DELAY SYSREF CD DELAY 0 0 0 0 SYNCb AB EN SYNCb CD EN 1 1
5 ANALOG SLEEP MODES – ENABLE PIN
6 ANALOG SLEEP MODES – SPI SYSREFCD EN
7 0 0 0 0 0 0 CLK SW AB 1 0 1 0 0 0 1 0 0
8 0 0 0 0 0 0 CLK SW CD 1 0 1 0 0 0 1 0 0
C 0 0 1 1 0 0 0 1 1 1 SYSREF JESD MODE CD SYSREF JESD MODE AB
D 0 0 0 0 0 0 JESD INIT CD JESD RESET CD 0 0 0 0 0 0 JESD INIT AB JESD RESET AB
E 0 0 0 0 0 0 0 0 TX LANE EN CD TX LANE EN AB
F 0 0 0 0 0 0 CTRL F AB 0 0 0 0 0 0 CTRL M AB
10 0 0 0 0 0 0 CTRL K AB 0 0 0 CTRL L AB
13 0 0 0 0 0 0 0 0 0 INV SYNCb AB HD AB SCR EN AB 0 0 0 0
16 0 0 0 0 0 0 CTRL F CD 0 0 0 0 0 0 CTRL M CD
17 0 0 0 0 0 0 CTRL K CD 0 0 0 CTRL L CD
1A 0 0 0 0 0 0 0 0 0 INV SYNCb CD HD CD SCR EN CD 0 0 0 0
1D 0 0 0 0 0 0 0 0 0 TEST PATTERN EN CD TEST PATTERN EN AB 0 TEST PATTERN 0 0 0
1E 0 0 0 0 0 0 JESD SLEEP MODES – ENABLE PIN
1F 1 1 1 1 1 1 JESD SLEEP MODES – SPI
20 JESD LANE POLARITY INVERT PRBS EN
21 0 PRBS SEL 0 0 0 0 0 0 0 0 0 0 VREF SEL
63 0 0 0 0 0 0 0 TEMP SENSOR
64 PRE EMP SEL AB PRE EMP EN AB DCC EN AB 0 0 0 0
67 OUTPUT CURRENT CONTROL AB
68 PRE EMP SEL CD PRE EMP EN CD DCC EN CD 0 0 0 0
6B OUTPUT CURRENT CONTROL CD
6C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JESD PLL CD JESD PLL AB