ZHCSD79A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
The ADS54J54 clock input can be driven differentially with a sine wave or LVPECL source with little or no difference in performance. The common mode voltage of the clock input is set to 0.9 V using internal 2-kΩ resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as possible to the clock inputs in order to minimize signal reflections and jitter degradation.