ZHCSD79A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLY | |||||||
IAVDD33 | 3.3-V analog supply current | 500 | mA | ||||
IAVDD18 | 1.9-V analog supply current | 320 | mA | ||||
IAVDDC | 1.8-V clock supply current | 18 | mA | ||||
IDVDD | 1.8-V digital supply current | 4-channel decimation filter | 323 | mA | |||
4-channel bypass digital mode | 324 | ||||||
2-channel decimation filter, 2-channel bypass digital mode | 324 | ||||||
IIOVDD | I/O voltage supply current | 2 lanes per ADC | 373 | mA | |||
1 lane per ADC | 185 | ||||||
IPLLVDD | PLL voltage supply current | 42 | mA | ||||
Pdis | Total power dissipation | 4-channel bypass digital mode | 3.46 | 3.7 | W | ||
4-channel decimation filter | 3.34 | ||||||
4-channel decimation filter, 1 lane per ADC | 3.27 | ||||||
2-channel decimation filter, 2-channel bypass digital mode | 3.51 | ||||||
Deep sleep mode power | 791 | mW | |||||
Wake-up time from deep sleep mode | SNR > 60 dB | 1.4 | ms | ||||
Light sleep mode power | 1.68 | W | |||||
Wake-up time from light sleep mode | SNR > 60 dB | 8 | µs | ||||
ANALOG INPUTS | |||||||
Differential input full-scale | 1 | 1.25 | 1.5 | Vpp | |||
Input common mode voltage | VCM ± 50 mV | V | |||||
Input resistance | Differential at DC | 1 | kΩ | ||||
Input capacitance | Each input to GND | 2.75 | pF | ||||
VCM | Common mode voltage output | 2.18 | V | ||||
Analog input bandwidth (–3 dB) | 900 | MHz | |||||
INL | Integral nonlinearity | ±3 | LSB | ||||
DNL | Dynamic nonlinearity | –1 | ±0.9 | LSB | |||
Gain error | ±2.24% | ||||||
Offset error | ±1.91 | mV | |||||
CHANNEL-TO-CHANNEL ISOLATION | |||||||
Crosstalk(1) | Near channel | ƒIN = 170 MHz | 85 | dB | |||
Far channel | ƒIN = 170 MHz | 95 | |||||
CLOCK INPUT | |||||||
Input clock frequency | 250 | 2000(2) | MHz | ||||
Input clock amplitude | 0.4 | 1.5 | Vpp | ||||
Input clock duty cycle | 45% | 50% | 55% | ||||
Internal clock biasing | 0.9 | V |