ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
Each transfer controller on the device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), and so forth. The parameters that determine the transfer controller configurations are:
All four parameters listed above are fixed by the design of the device.
Table 8-33 shows the configuration of each of the EDMA3 transfer controllers present on the device.
PARAMETER | EDMA3 CC0/CC4 | EDMA3 CC1 | EDMA3 CC2 | EDMA3CC3 | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
TC0 | TC1 | TC0 | TC1 | TC2 | TC3 | TC0 | TC1 | TC2 | TC3 | TC0 | TC1 | |
FIFOSIZE | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes |
BUSWIDTH | 32 bytes | 32 bytes | 16 bytes | 16 bytes | 16 bytes | 16 bytes | 16 bytes | 16 bytes | 16 bytes | 16 bytes | 16 bytes | 16 bytes |
DSTREGDEPTH | 4 entries | 4 entries | 4 entries | 4 entries | 4 entries | 4 entries | 4 entries | 4 entries | 4 entries | 4 entries | 4 entries | 4 entries |
DBS | 128 bytes | 128 bytes | 128 bytes | 128 bytes | 128 bytes | 128 bytes | 128 bytes | 128 bytes | 128 bytes | 128 bytes | 64 bytes | 64 bytes |