ZHCSBT2G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
      1. 1.3.1 KeyStone II 的增强功能
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. 6 C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
      1. Table 6-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    7. 6.7 C66x CorePac Register Descriptions
  7. 7 ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. 8 Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
            1. Table 8-9 Configuration Register Field Descriptions
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 8-10 Programmable Range n Start Address Register Field Descriptions
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
          1. Table 8-14 Programmable Range n End Address Register Field Descriptions
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
          1. Table 8-18 Programmable Range n Memory Protection Page Attribute Register Field Descriptions
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
          1. Table 10-3 Boot Mode Pins: Boot Device Values
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
            1. Table 10-4 Sleep Boot Configuration Field Descriptions
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
              1. Table 10-5 I2C Passive Mode Device Configuration Field Descriptions
            2. 10.1.2.2.2.2 I2C Master Mode
              1. Table 10-6 I2C Master Mode Device Configuration Field Descriptions
          3. 10.1.2.2.3 SPI Boot Device Configuration
            1. Table 10-7 SPI Device Configuration Field Descriptions
          4. 10.1.2.2.4 EMIF Boot Device Configuration
            1. Table 10-8 EMIF Boot Device Configuration Field Descriptions
          5. 10.1.2.2.5 NAND Boot Device Configuration
            1. Table 10-9 NAND Boot Device Configuration Field Descriptions
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
          1. Table 10-10 Serial Rapid I/O Boot Device Configuration Field Descriptions
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. Table 10-11 Ethernet (SGMII) Boot Device Configuration Field Descriptions
          2. 10.1.2.4.1   PCIe Boot Device Configuration
            1. Table 10-12 PCIe Boot Device Configuration Field Descriptions
          3. 10.1.2.4.2   HyperLink Boot Device Configuration
            1. Table 10-14 HyperLink Boot Device Configuration Field Descriptions
          4. 10.1.2.4.3   UART Boot Device Configuration
            1. Table 10-15 UART Boot Configuration Field Descriptions
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
          1. Table 10-31 Device Status Register Field Descriptions
        2. 10.2.3.2  Device Configuration Register
          1. Table 10-32 Device Configuration Register Field Descriptions
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
          1. Table 10-33 JTAG ID Register Field Descriptions
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
          1. Table 10-1 DSP BOOT Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
          1. Table 10-35 LRESETNMI PIN Status Register Field Descriptions
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
          1. Table 10-36 LRESETNMI PIN Status Clear Register Field Descriptions
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
          1. Table 10-37 Reset Status Register Field Descriptions
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
          1. Table 10-38 Reset Status Clear Register Field Descriptions
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
          1. Table 10-39 Boot Complete Register Field Descriptions
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
          1. Table 10-40 Power State Control Register Field Descriptions
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
          1. Table 10-41 NMI Generation Register Field Descriptions
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
          1. Table 10-42 IPC Generation Registers Field Descriptions
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
          1. Table 10-43 IPC Acknowledgment Registers Field Descriptions
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
          1. Table 10-44 IPC Generation Registers Field Descriptions
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
          1. Table 10-45 IPC Acknowledgment Register Field Descriptions
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
          1. Table 10-46 Timer Input Selection Field Description
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
          1. Table 10-47 Timer Output Selection Register Field Descriptions
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
          1. Table 10-48 Reset Mux Register Field Descriptions
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
          1. Table 10-49 Device Speed Register Field Descriptions
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
          1. Table 10-50 ARM Endian Configuration Register 0 Field Descriptions
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
          1. Table 10-51 ARM Endian Configuration Register 1 Field Descriptions
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
          1. Table 10-52 ARM Endian Configuration Register 2 Field Descriptions
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
          1. Table 10-53 Chip Miscellaneous Control Register Field Descriptions
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
          1. Table 10-54 Chip Miscellaneous Control Register Field Descriptions
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
          1. Table 10-55 System Endian Status Register Field Descriptions
        27. 10.2.3.27 SYNECLK_PINCTL Register
          1. Table 10-56 SYNECLK_PINCTL Register Field Descriptions
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
          1. Table 10-57 USB_PHY_CTL0 Register Field Descriptions
          2. Table 10-58 USB_PHY_CTL1 Register Field Descriptions
          3. Table 10-59 USB_PHY_CTL2 Register Field Descriptions
          4. Table 10-60 USB_PHY_CTL3 Register Field Descriptions
          5. Table 10-61 USB_PHY_CTL4 Register Field Descriptions
          6. Table 10-62 USB_PHY_CTL5 Register Field Descriptions
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
        1. Table 11-5 SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
        1. Table 11-10 Reset Timing Requirements
        2. Table 11-11 Reset Switching Characteristics
        3. Table 11-12 Boot Configuration Timing Requirements
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 11-16 PLL Secondary Control Register Field Descriptions
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
          1. Table 11-17 PLL Controller Divider Register Field Descriptions
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 11-18 PLL Controller Clock Align Control Register Field Descriptions
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 11-19 PLLDIV Divider Ratio Change Status Register Field Descriptions
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 11-20 SYSCLK Status Register Field Descriptions
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 11-21 Reset Type Status Register Field Descriptions
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 11-22 Reset Control Register Field Descriptions
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 11-23 Reset Configuration Register Field Descriptions
        9. 11.5.2.9 Reset Isolation Register (RSISO)
          1. Table 11-24 Reset Isolation Register Field Descriptions
      3. 11.5.3 Main PLL Control Registers
        1. Table 11-25 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 11-26 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 11.5.4 ARM PLL Control Registers
        1. Table 11-27 ARM PLL Control Register 0 Field Descriptions
        2. Table 11-28 ARM PLL Control Register 1 Field Descriptions
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
        1. Table 11-29 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Timing Requirements
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
        1. Table 11-30 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions
        2. Table 11-31 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
        1. Table 11-32 DDR3 PLL DDRCLK(N|P) Timing Requirements
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
        1. Table 11-33 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
        2. Table 11-34 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
        1. Table 11-35 PASS PLL Timing Requirements
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
        1. Table 11-36 NMI and LRESET Timing Requirements
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
        1. Table 11-38 I2C Timing Requirements
        2. Table 11-39 I2C Switching Characteristics
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
        1. Table 11-40 SPI Timing Requirements
        2. Table 11-41 SPI Switching Characteristics
    12. 11.12 HyperLink Peripheral
      1. Table 11-42 HyperLink Peripheral Timing Requirements
      2. Table 11-43 HyperLink Peripheral Switching Characteristics
    13. 11.13 UART Peripheral
      1. Table 11-44 UART Timing Requirements
      2. Table 11-45 UART Switching Characteristics
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
      1. Table 11-46 MACID1 Register Field Descriptions
      2. Table 11-47 MACID2 Register Field Descriptions
      3. Table 11-48 RFTCLK Select Register Field Descriptions
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
      1. Table 11-49 MDIO Timing Requirements
      2. Table 11-50 MDIO Switching Characteristics
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
        1. Table 11-51 Timer Input Timing Requirements
        2. Table 11-52 Timer Output Switching Characteristics
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
        1. Table 11-54 GPIO Input Timing Requirements
        2. Table 11-55 GPIO Output Switching Characteristics
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
        1. Table 11-56 EMIF16 Asynchronous Memory Timing Requirements
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
          1. Table 11-66 Trace Switching Characteristics
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
          1. Table 11-67 JTAG Test Port Timing Requirements
          2. Table 11-68 JTAG Test Port Switching Characteristics
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • AAW|1517
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.2 Pin Map

The following figures show the 66AK2Hxx pin assignments in four quadrants (A, B, C, and D). The 14 pins serving the 10-GbE function (XFI) in the 66AK2H14 device are reserved in the 66AK2H12/06 devices.

66AK2H14 66AK2H12 66AK2H06 Pin_Map_Panels.gifFigure 4-2 Pin Map Panels (Bottom View)
1 2 3 4 5 6 7 8 9 10
AW (NOPIN) VSS VSS HYP1CLKP HYP1CLKN VSS HYP0RXN3 HYP0RXP3 VSS HYP0RXN0
AV VSS VSS HYP1RXN3 HYP1RXP3 VSS HYP1RXN1 HYP1RXP1 VSS HYP0RXN2 HYP0RXP2
AU VSS VSS VSS HYP1RXN2 HYP1RXP2 VSS HYP1RXN0 HYP1RXP0 VSS HYP0RXN1
AT RSV190 VSS HYP1TXN3 HYP1TXP3 VSS HYP1TXN0 HYP1TXP0 VSS HYP0CLKP HYP0CLKN
AR RSV189 RSV186 VSS HYP1TXN2 HYP1TXP2 VSS HYP0TXN3 HYP0TXP3 VSS HYP0TXN1
AP TSRXCLKOUT0N RSV187 TSRXCLKOUT1N VSS HYP1TXN1 HYP1TXP1 VSS HYP0TXN2 HYP0TXP2 VSS
AN TSRXCLKOUT0P VSS TSRXCLKOUT1P RSV002 VSS VSS VSS VSS VSS RSV019
AM TSREFCLKP ALTCORECLKP VSS RSV003 CVDD HYP1REFRES RSV020 VSS HYP0REFRES VSS
AL TSREFCLKN ALTCORECLKN SYSCLKP CORECLKSEL VSS CVDD VSS CVDD VSS VDDAHV
AK SYSCLKOUT VSS SYSCLKN POR RSV012 VSS CVDD VSS CVDD VSS
AJ HYP0TXPMDAT HYP0RXPMCLK HYP0TXFLCLK HYP0RXFLDAT HYP0RXFLCLK VSS VSS CVDD VSS CVDD
AH HYP1TXPMCLK HYP1TXFLDAT HYP1TXFLCLK HYP1RXFLCLK HYP0TXPMCLK VSS VSS VSS CVDD VSS
AG TDI HYP1RXFLDAT HYP0RXPMDAT VSS HYP0TXFLDAT DVDD18 VSS CVDD VSS CVDD
AF TDO HYP1TXPMDAT HYP1RXPMCLK HYP1RXPMDAT BOOTCOMPLETE VSS DVDD18 VSS CVDD VSS
AE TCK TMS VSS LRESET HOUT DVDD18 VSS CVDD VSS CVDD
AD TRST RESET RESETFULL LRESETNMIEN NMI VSS DVDD18 VSS CVDD VSS
AC TSPUSHEVT1 TSPUSHEVT0 TSSYNCEVT RSV188 RESETSTAT DVDD18 VSS CVDD VSS CVDD
AB TSCOMPOUT EMU01 EMU14 EMU10 DVDD18 VSS DVDD18 VSS CVDD VSS
AA USBRESREF EMU00 EMU11 EMU18 VSS DVDD18 VSS CVDD VSS CVDD
Y USBRX0M VSS EMU02 EMU03 DVDD18 VSS DVDD18 VSS CVDD VSS
W USBRX0P USBCLKP EMU04 EMU05 VSS DVDD18 VSS CVDD VSS CVDD
V USBTX0M USBCLKM VSS EMU06 DVDD18 VSS DVDD18 VSS CVDD VSS
U USBTX0P USBDP EMU08 EMU07 EMU12 DVDD18 VSS CVDD VSS CVDD
T USBVBUS USBDM EMU09 EMU13 EMU16 VSS DVDD18 VSS CVDD VSS
R USBID0 VSS EMU15 EMU17 VSS DVDD18 VSS CVDD VSS CVDD
P RSV001 RSV000 SDA0 SCL2 VSS VSS CVDD VSS CVDD VSS
N SCL0 SDA1 SDA2 SCL1 VSS CVDD VSS CVDD VSS CVDD
M TIMI1 TIMI0 TIMO0 TIMO1 UART1RTS VSS CVDD VSS CVDD VSS
L UART0CTS UART1RXD USBDRVVBUS UART0RTS VSS CVDD VSS DVDD15 VSS DVDD15
K UART1CTS UART0TXD UART1TXD UART0RXD VSS VSS DVDD15 VSS DVDD15 VSS
J VSS VSS VSS VSS VSS DVDD15 VSS DVDD15 VSS DVDD15
H DDR3AD04 DDR3AD01 DDR3AD13 VSS DDR3AD17 VSS DVDD15 VSS DVDD15 DDR3ARQ1
G DDR3AD00 DDR3AD03 DDR3AD10 DDR3AD16 DDR3AD20 DDR3AD29 DDR3AD30 DDR3AA02 DDR3AA01 DDR3AA03
F DDR3AD02 DDR3AD06 DDR3ADQM1 DDR3AD09 DDR3AD19 DDR3AD26 DDR3AD25 DDR3AA05 DDR3AA04 DDR3AA10
E DDR3ADQS0P DDR3AD05 VSS DDR3AD08 VSS DDR3ADQM3 VSS DDR3AA00 VSS DDR3AA12
D DDR3ADQS0N DDR3AD07 DDR3AD14 DDR3AD15 DDR3AD18 DDR3AD21 DDR3AD31 DDR3AA09 DDR3AA07 DDR3AA15
C VSS DDR3ADQM0 DDR3ADQS1N VSS DDR3AD22 VSS DDR3AD24 VSS DDR3AA06 VSS
B VSS VSS DDR3ADQS1P DDR3AD12 DDR3ADQS2N DDR3AD23 DDR3ADQS3P DDR3AD28 DDR3AA08 DDR3AA14
A (NOPIN) VSS VSS DDR3AD11 DDR3ADQS2P DDR3ADQM2 DDR3ADQS3N DDR3AD27 DDR3AA11 DDR3AA13
1 2 3 4 5 6 7 8 9 10
Figure 4-3 66AK2Hxx Pin Map Left Side Panel (A) — Bottom View
11 12 13 14 15 16 17 18 19 20
AW HYP0RXP0 VSS RSV167 RSV168 VSS RSV161 RSV162 VSS XFIRXP1 XFIRXN1
AV VSS RSV171 RSV172 VSS RSV165 RSV166 VSS XFIRXP0 XFIRXN0 VSS
AU HYP0RXP1 VSS RSV169 RSV170 VSS RSV163 RSV164 VSS XFICLKP XFICLKN
AT VSS RSV183 RSV184 VSS RSV177 RSV178 VSS XFITXP0 XFITXN0 VSS
AR HYP0TXP1 VSS RSV181 RSV182 VSS RSV175 RSV176 VSS XFITXP1 XFITXN1
AP HYP0TXN0 HYP0TXP0 VSS RSV179 RSV180 VSS RSV173 RSV174 VSS VSS
AN VSS VSS VSS VSS VSS XFIREFRES0 VSS VSS RSV026 VSS
AM RSV099 VSS VSS RSV025 RSV185 RSV024 VSS VSS XFIREFRES1 VSS
AL VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV
AK VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS VDDAHV VSS
AJ VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV
AH VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS
AG VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV
AF AVDDA1 VSS VDDALV VSS VDDALV VSS VDDALV VSS VDDALV VSS
AE VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD
AD VNWA2 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS
AC VSS CVDD VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD
AB CVDD VSS VDDUSB VSS CVDD VSS CVDD VSS CVDD VSS
AA VSS VP VSS DVDD33 VSS CVDD VSS CVDD VSS CVDD
Y VPTX VSS VPH VSS CVDD VSS CVDD VSS CVDD VSS
W VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD VSS CVDD
V VNWA4 VSS CVDD1 VSS CVDD VSS CVDD1 VSS CVDD VSS
U VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD1
T CVDD VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS
R VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS CVDD
P AVDDA6 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS
N VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS AVDDA2
M DVDD15 VSS AVDDA7 VSS AVDDA8 VSS DVDD15 AVDDA9 DVDD15 AVDDA10
L VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15
K DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS
J VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15
H DVDD15 VSS DVDD15 VSS DVDD15 DDR3ARQ0 DVDD15 VSS DVDD15 VSS
G DDR3ABA2 DDR3ACKE0 DDR3AODT1 DDR3AVREFSSTL DDR3ACB07 DDR3AD33 DDR3AD35 DDR3AD42 DDR3AD44 DDR3AD51
F DDR3ACE1 DDR3AWE RSV029 DDR3ACB05 DDR3ACB03 DDR3AD34 DDR3AD38 DDR3AD47 DDR3AD43 DDR3AD54
E VSS DDR3AODT0 VSS DDR3ADQM8 VSS DDR3AD32 VSS DDR3AD39 VSS DDR3AD53
D DDR3ACE0 RSV027 RSV028 DDR3ACB06 DDR3ACB04 DDR3AD36 DDR3AD37 DDR3AD46 DDR3AD41 DDR3AD50
C DDR3ABA1 VSS DDR3ACAS VSS DDR3ACB01 VSS DDR3ADQM4 VSS DDR3AD40 VSS
B DDR3ABA0 DDR3ACLKOUTN0 DDR3ACLKOUTN1 DDR3ARESET DDR3ADQS8P DDR3ACB02 DDR3ADQS4N DDR3AD45 DDR3ADQS5P DDR3AD49
A DDR3ACKE1 DDR3ACLKOUTP0 DDR3ACLKOUTP1 DDR3ARAS DDR3ADQS8N DDR3ACB00 DDR3ADQS4P DDR3ADQM5 DDR3ADQS5N DDR3AD48
11 12 13 14 15 16 17 18 19 20
Figure 4-4 66AK2Hxx Pin Map Left Center Panel (B) — Bottom View
21 22 23 24 25 26 27 28 29 30
VSS RIORXN2 RIORXP2 VSS SGMII3RXN SGMII3RXP VSS SGMII0RXN SGMII0RXP VSS AW
RIORXN3 RIORXP3 VSS RIORXN0 RIORXP0 VSS SGMII1RXN SGMII1RXP VSS PCIERXN1 AV
VSS RIORXN1 RIORXP1 VSS SGMII2RXN SGMII2RXP VSS SGMII0TXN SGMII0TXP VSS AU
RIOTXN3 RIOTXP3 VSS RIOTXN0 RIOTXP0 VSS SGMII1TXN SGMII1TXP VSS PCIETXN0 AT
VSS VSS RIOTXN1 RIOTXP1 VSS SGMII2TXN SGMII2TXP VSS PCIETXN1 PCIETXP1 AR
VSS RIOTXN2 RIOTXP2 VSS SGMII3TXN SGMII3TXP VSS VSS VSS VSS AP
VSS VSS VSS VSS VSS VSS VSS VSS VSS PACLKSEL AN
RIOREFRES VSS RSV021 SGMIIREFRES RSV023 PCIEREFRES DVDD18 RSV022 DVDD18 RSV192 AM
VSS VDDAHV VSS VDDAHV VSS DVDD18 VSS DVDD18 VSS CVDD AL
VDDAHV VSS VDDAHV VSS VDDAHV VSS DVDD18 VSS CVDD VSS AK
VSS VDDALV VSS VDDALV VSS DVDD18 VSS CVDD VSS DVDD15 AJ
VDDALV VSS VDDALV VSS VDDALV VSS CVDD VSS AVDDA4 VSS AH
VSS VDDALV VSS VNWA1 VSS AVDDA5 VSS CVDD VSS DVDD15 AG
VDDALV VSS VDDALV VSS CVDD VSS CVDD VSS DVDD15 VSS AF
VSS CVDD VSS CVDD VSS CVDD VSS AVDDA15 VSS DVDD15 AE
CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA14 DVDD15 VSS AD
VSS CVDD VSS CVDD VSS CVDD VSS AVDDA13 VSS DVDD15 AC
CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA12 DVDD15 VSS AB
VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 AA
CVDD VSS CVDD VSS CVDD VSS CVDD AVDDA11 DVDD15 VSS Y
VSS CVDDT1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 W
CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS V
VSS CVDDT1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 U
CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS T
VSS CVDDT1 VSS CVDD VSS CVDD VSS DVDD15 VSS DVDD15 R
CVDD VSS CVDD VSS CVDD VSS CVDD VSS DVDD15 VSS P
VSS CVDD VSS CVDD VSS CVDD VSS AVDDA3 VSS DVDD18 N
VPP VSS VNWA3 VSS CVDD VSS CVDD VSS DVDD18 VSS M
VSS VPP VSS DVDD18 VSS DVDD18 VSS CVDD VSS DVDD18 L
DVDD15 VSS DVDD15 VSS DVDD18 VSS DVDD18 VSS CVDD VSS K
VSS DVDD15 VSS VSS VSS DVDD18 VSS DVDD18 VSS CVDD J
DVDD15 DDR3ARQ2 DVDD15 VSS DVDD18 VSS DVDD18 VSS VSS VSS H
DDR3AD55 DDR3AD57 VSS CORESEL3 VSS RSV018 VSS SPI2DOUT VSS GPIO09 G
DDR3AD62 DDR3AD59 RSV013 CORESEL0 SPI0SCS0 RSV017 SPI1DIN SPI2DIN GPIO00 GPIO12 F
VSS DDR3AD60 RSV014 CORESEL1 SPI2SCS3 SPI0SCS2 SPI1SCS3 VSS GPIO05 GPIO11 E
DDR3ADQM6 DDR3AD63 DDR3AD58 CORESEL2 SPI2CLK SPI0SCS3 SPI1SCS2 SPI2SCS1 GPIO02 GPIO06 D
DDR3AD52 VSS DDR3AD56 VSS SPI0SCS1 VSS SPI1SCS1 SPI1CLK VSS GPIO07 C
DDR3ADQS6N DDR3AD61 DDR3ADQS7N RSV004 DDR3ACLKP SPI0CLK SPI1SCS0 SPI2SCS0 GPIO04 GPIO01 B
DDR3ADQS6P DDR3ADQM7 DDR3ADQS7P RSV005 DDR3ACLKN SPI0DIN SPI0DOUT SPI1DOUT SPI2SCS2 GPIO08 A
21 22 23 24 25 26 27 28 29 30
Figure 4-5 66AK2Hxx Pin Map Right Center Panel (C) — Bottom View
31 32 33 34 35 36 37 38 39
PCIECLKP PCIECLKN VSS SRIOSGMIICLKP SRIOSGMIICLKN RSV81 VSS VSS (NOPIN) AW
PCIERXP1 VSS PASSCLKP PASSCLKN VSS RSV79 RSV77 VSS VSS AV
PCIERXN0 PCIERXP0 VSS RSV008 RSV80 RSV76 RSV78 VCNTL4 VSS AU
PCIETXP0 VSS XFIMDIO RSV009 RSV75 VSS RSV74 VCNTL3 VCNTL0 AT
VSS MDIO VSS XFIMDCLK VCNTL5 VCNTL2 VCNTL1 DDR3BCLKP DDR3BCLKN AR
MDCLK RSV193 RSV195 RSV191 VD VCL VSS RSV006 RSV007 AP
VSS RSV194 DDR3BD58 DDR3BD56 VSS DDR3BD57 DDR3BD63 DDR3BDQS7P DDR3BDQS7N AN
CVDD VSS VSS DDR3BD59 DDR3BD60 DDR3BD62 VSS DDR3BD61 DDR3BDQM7 AM
VSS DVDD15 DDR3BD55 DDR3BD52 VSS DDR3BD53 DDR3BD54 DDR3BDQS6N DDR3BDQS6P AL
DVDD15 DDR3BRQ2 VSS DDR3BDQM6 DDR3BD51 DDR3BD50 VSS DDR3BD49 DDR3BD48 AK
VSS VSS DDR3BD41 DDR3BD43 VSS DDR3BD44 DDR3BD47 DDR3BDQS5N DDR3BDQS5P AJ
DVDD15 DDR3BD40 VSS DDR3BD37 DDR3BD38 DDR3BD42 VSS DDR3BD46 DDR3BD45 AH
VSS DDR3BD39 DDR3BDQM4 DDR3BD35 VSS DDR3BD36 DDR3BD32 DDR3BD34 DDR3BDQM5 AG
DVDD15 DDR3BCB00 VSS DDR3BCB01 DDR3BCB03 DDR3BD33 VSS DDR3BDQS4P DDR3BDQS4N AF
VSS DDR3BCB02 DDR3BCB04 DDR3BCB07 VSS DDR3BCB05 DDR3BDQM8 DDR3BDQS8N DDR3BDQS8P AE
DVDD15 DDR3BRAS VSS DDR3BODT1 RSV030 DDR3BCB06 VSS DDR3BCLKOUTP0 DDR3BCLKOUTN0 AD
DDR3BVREFSSTL DDR3BRESET DDR3BODT0 RSV031 VSS DDR3BCAS DDR3BWE DDR3BCLKOUTN1 DDR3BCLKOUTP1 AC
DVDD15 RSV032 VSS DDR3BCE0 DDR3BBA2 VSS VSS DDR3BCKE1 DDR3BCKE0 AB
DDR3BRQ0 DDR3BA00 DDR3BA08 DDR3BBA1 VSS DDR3BCE1 DDR3BBA0 DDR3BA14 DDR3BA11 AA
DVDD15 DDR3BA09 VSS DDR3BA03 DDR3BA12 DDR3BA15 VSS DDR3BA10 DDR3BA13 Y
VSS DDR3BA02 DDR3BA01 DDR3BA04 VSS DDR3BA06 DDR3BA07 DDR3BD27 DDR3BD28 W
DVDD15 DDR3BD30 VSS DDR3BA05 DDR3BD24 DDR3BD31 VSS DDR3BDQS3N DDR3BDQS3P V
VSS DDR3BDQM3 DDR3BD29 DDR3BD26 VSS DDR3BD25 DDR3BD21 DDR3BD23 DDR3BDQM2 U
DVDD15 DDR3BD08 VSS DDR3BD16 DDR3BD18 DDR3BD22 VSS DDR3BDQS2N DDR3BDQS2P T
VSS DDR3BD09 DDR3BD14 DDR3BD17 VSS DDR3BD20 DDR3BD19 DDR3BD12 DDR3BD11 R
DVDD15 DDR3BRQ1 VSS DDR3BDQM1 DDR3BD10 DDR3BD15 VSS DDR3BDQS1N DDR3BDQS1P P
VSS DDR3BD13 DDR3BD04 DDR3BD01 VSS DDR3BD06 DDR3BD05 DDR3BD07 DDR3BDQM0 N
DVDD15 EMIFD00 VSS EMIFD13 EMIFD15 EMIFD14 DDR3BD02 DDR3BDQS0P DDR3BDQS0N M
VSS DVDD15 EMIFD02 EMIFD03 EMIFD12 EMIFD11 VSS DDR3BD00 DDR3BD03 L
DVDD18 VSS EMIFA07 EMIFA16 VSS EMIFD10 EMIFD06 EMIFD09 EMIFD08 K
VSS DVDD18 VSS EMIFA05 EMIFA18 EMIFA21 EMIFD01 EMIFD05 EMIFD07 J
CVDD VSS EMIFBE1 EMIFBE0 EMIFA06 EMIFA12 VSS EMIFA22 EMIFD04 H
VSS EMIFCE1 EMIFCE0 EMIFCE2 VSS EMIFA02 EMIFA09 EMIFA14 EMIFA19 G
GPIO10 RSV016 EMIFRNW EMIFA00 EMIFA17 EMIFWE EMIFA01 EMIFA10 EMIFA15 F
GPIO25 GPIO14 RSV015 EMIFA04 EMIFA13 EMIFCE3 EMIFOE EMIFWAIT0 EMIFA03 E
GPIO22 GPIO27 GPIO21 VSS EMIFA11 EMIFA23 VSS RSV011 EMIFWAIT1 D
GPIO18 VSS GPIO28 GPIO29 EMIFA08 EMIFA20 ARMCLKP RSV010 VSS C
GPIO15 GPIO19 GPIO24 GPIO31 GPIO23 GPIO30 ARMCLKN VSS VSS B
GPIO13 GPIO17 GPIO20 GPIO26 GPIO03 GPIO16 VSS VSS (NOPIN) A
31 32 33 34 35 36 37 38 39
Figure 4-6 66AK2Hxx Pin Map Right Side Panel (D) — Bottom View