ZHCSEC5D November   2015  – May 2021 TPS65235

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short Circuit Protection, Hiccup and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Disable and Enable
      10. 7.3.10 Component Selection
        1. 7.3.10.1 Boost Inductor
        2. 7.3.10.2 Capacitor Selection
        3. 7.3.10.3 Surge Components
        4. 7.3.10.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00H) [reset = 00010000]
      2. 7.6.2 Control Register 2 (address = 0x01H) [reset = 0000101]
      3. 7.6.3 Status Register (address = 0x02H) [reset = x0100000]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application for DiSEqc1.x Support
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application for DiSEqc2.x Support
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7.5.1 Serial Interface Description

I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high external. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The TPS65235 device works as a slave and supports the following data transfer modes, as defined in the I2CBus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 4.5 V (typical).

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The TPS65235 device supports 7-bit addressing; 10-bit addressing and general call address are not supported.

The TPS65235 device has a 7-bit address set by ADDR pin. Table 7-4 shows how to set the I2C address.

Table 7-4 I2C Address Selection
ADDR PINI2C ADDRESSAddress Format (A6 ≥ A0)
Connect to VCC0x08H000 1000
Floating0x09H000 1001
Connected to GND0x10H001 0000
Resistor divider to make ADDR pin voltage in 3 V ~ VCC - 0.8 V0x11H001 0001
GUID-2CCCDD09-714F-41DF-95AC-4870D77F0CAF-low.gifFigure 7-9 I2C Interface Timing Diagram