ZHCSRJ6C June   2010  – January 2023 TLV320AIC3104-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 8.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 8.8  Switching Characteristics DSP Timing in Master Mode
    9. 8.9  Switching Characteristics DSP Timing in Slave Mode
    10. 8.10 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Audio Data Converters
      2. 9.3.2  Stereo Audio ADC
        1. 9.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 9.3.3  Automatic Gain Control (AGC)
      4. 9.3.4  Stereo Audio DAC
      5. 9.3.5  Digital Audio Processing for Playback
      6. 9.3.6  Digital Interpolation Filter
      7. 9.3.7  Delta-Sigma Audio DAC
      8. 9.3.8  Audio DAC Digital Volume Control
      9. 9.3.9  Analog Output Common-mode Adjustment
      10. 9.3.10 Audio DAC Power Control
      11. 9.3.11 Audio Analog Inputs
      12. 9.3.12 Analog Input Bypass Path Functionality
      13. 9.3.13 ADC PGA Signal Bypass Path Functionality
      14. 9.3.14 Input Impedance and VCM Control
      15. 9.3.15 MICBIAS Generation
      16. 9.3.16 Analog Fully Differential Line Output Drivers
      17. 9.3.17 Analog High-Power Output Drivers
      18. 9.3.18 Short-Circuit Output Protection
      19. 9.3.19 Jack and Headset Detection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Audio Processing for Record Path
      2. 9.4.2 Increasing DAC Dynamic Range
      3. 9.4.3 Passive Analog Bypass During Power Down
      4. 9.4.4 Hardware Reset
    5. 9.5 Programming
      1. 9.5.1  Digital Control Serial Interface
      2. 9.5.2  I2C Control Interface
      3. 9.5.3  I2C Bus Debug in a Glitched System
      4. 9.5.4  Digital Audio Data Serial Interface
      5. 9.5.5  Right-Justified Mode
      6. 9.5.6  Left-Justified Mode
      7. 9.5.7  I2S Mode
      8. 9.5.8  DSP Mode
      9. 9.5.9  TDM Data Transfer
      10. 9.5.10 Audio Clock Generation
    6. 9.6 Register Maps
      1. 9.6.1 Output Stage Volume Controls
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 静电放电警告
  14. 14Mechanical, Packaging, and Orderable Information

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Analog Fully Differential Line Output Drivers

The TLV320AIC3104-Q1 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 9-5 and Figure 9-6. This design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond that already provided by the PGA gain and the DAC digital volume control.

The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC to the output stage. Note that because both left- and right-channel signals are routed to all output drivers, a mono mix of any of the stereo signals can easily be obtained by setting the volume controls of both left- and right\u0002channel signals to –6 dB and mixing them. Undesired signals can also be disconnected from the mix through register control

Figure 9-5 Architecture of Output Stage Leading to Fully-Differential Line Output Drivers
Figure 9-6 Detail of Volume Control and Mixing Function

The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based on the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC output is only needed at the stereo line outputs, then it is recommended to use the routing through path DAC_L3/R3 to the fully differential stereo line outputs. This results not only in higher-quality output performance, but also in lower-power operation, because the analog volume controls and mixing blocks ahead of these drivers can be powered down.

If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as to LEFT_LOP/M and RIGHT_LOP/M) or must be mixed with other analog signals, then the DAC outputs should be switched through the DAC_L1/R1 path. This option provides the maximum flexibility for routing of the DAC analog signals to the output drivers.

The TLV320AIC3104-Q1 includes an output level control on each output driver with limited gain adjustment from 0 dB to 9 dB. The output driver circuitry in this device is designed to provide a low-distortion output while playing full-scale stereo DAC signals at a 0-dB gain setting. However, a higher amplitude output can be obtained at the cost of increased signal distortion at the output. This output level control allows the user to make this tradeoff based on the requirements of the end equipment. Note that this output level control is not intended to be used as a standard output volume control. It is expected to be used only sparingly for level setting, i.e., adjustment of the full-scale output range of the device.

Each differential line output driver can be powered down independently of the others when it is not needed in the system. When placed into power down through register programming, the driver output pins are placed into a high-impedance state.