The TLIN1441-Q1 LIN transceiver is a Local Interconnect Network (LIN) physical layer transceiver, compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 with integrated wake-up and protection features. The LIN bus is a single-wire, bidirectional bus that typically is used in low-speed in-vehicle networks with data rates that range up to 20 kbps. The LIN receiver works up to 100 kbps supporting in-line programming. The device converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited wave-shaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic-level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode.

Ultra-low current consumption is possible using the sleep mode. The TLIN1441-Q1 provides three methods to wake up from sleep mode: EN pin, WAKE pin and LIN bus. The device integrates a low dropout voltage regulator with a wide input from V_SUP providing 5 V ±2% or 3.3 V ±2% with up to 125 mA of current depending upon system implementation.

The TLIN1441-Q1 integrates a window based watchdog supervisor which has a programmable delay and window ratio determined by pin strapping or SPI communication. The device watchdog is controlled by pin configuration or SPI depending upon the state of pin 9 at power up. At power up, if pin 9 is externally pulled to ground, the device is configured for pin control of the device. If pin 9 is connected to the nCS pin of the processors and not driven at power up, the internal pull up configures the device for 3.3 V SPI control. If the processor uses 5 V IO a 500k Ω pull up resistor to V_CC is used for the 5 V version of the device. This allows the 5 V version of the device to work with both 3.3 V SPI or 5 V SPI. SPI communication is used for device configuration. In pin configuration nRST is asserted high when V_CC increases above UV_CC and stays high as long as V_CC is above this threshold.

When the watchdog is controlled by the device pins, the state of the WDT pin determines the window time. WDI is used as the watchdog input trigger which is expected in the open window. If a watchdog event takes place, the nWDR pin goes low to reset the processors. When using SPI writing FFh to register 15h, WD_TRIG, during the open window restarts the watchdog timer. The supervised processor must trigger the WDI pin or WD_TRIG register within the defined window. When using SPI, the nRST pin becomes the watchdog event output trigger for the processor. The watchdog timer does not start until after the first input trigger on WDI or the WD_TRIG register.