ZHCSJ16D November   2018  – June 2022 TLIN1441-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings, IEC Specification
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Power Supply Characteristics
    7. 7.7 Electrical Characteristics
    8. 7.8 AC Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuit: Diagrams and Waveforms
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN Pin
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD (Transmit Input)
      3. 9.3.3  RXD (Receive Output)
      4. 9.3.4  WAKE (High Voltage Local Wake Up Input)
      5. 9.3.5  WDT/CLK (Pin Programmable Watchdog Delay Input/SPI Clock)
      6. 9.3.6  WDI/SDI (Watchdog Timer Input/SPI Serial Data In)
      7. 9.3.7  PIN/nCS (Pin Watchdog Select/SPI Chip Select)
      8. 9.3.8  LIMP (LIMP Home output – High Voltage Open Drain Output)
      9. 9.3.9  nWDR/SDO (Watchdog Timeout Reset Output/SPI Serial Data Out)
      10. 9.3.10 VSUP (Supply Voltage)
      11. 9.3.11 GND (Ground)
      12. 9.3.12 EN/nINT (Enable Input/Interrupt Output in SPI Mode)
      13. 9.3.13 nRST/nWDR (Reset Output/Watchdog Timeout Reset Output)
      14. 9.3.14 VCC (Supply Output)
      15. 9.3.15 Protection Features
        1. 9.3.15.1 TXD Dominant Time Out (DTO)
        2. 9.3.15.2 Bus Stuck Dominant System Fault: False Wake Up Lockout
        3. 9.3.15.3 Thermal Shutdown
        4. 9.3.15.4 Under Voltage on VSUP
        5. 9.3.15.5 Unpowered Device and LIN Bus
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Failsafe Mode
      5. 9.4.5 Wake-Up Events
        1. 9.4.5.1 Wake-Up Request (RXD)
        2. 9.4.5.2 Local Wake Up (LWU) via WAKE Terminal
      6. 9.4.6 Mode Transitions
      7. 9.4.7 Voltage Regulator
        1. 9.4.7.1 VCC
        2. 9.4.7.2 Output Capacitance Selection
        3. 9.4.7.3 Low-Voltage Tracking
        4. 9.4.7.4 Power Supply Recommendation
      8. 9.4.8 Watchdog
        1. 9.4.8.1 Watchdog Error Counter
        2. 9.4.8.2 Pin Control Mode
        3. 9.4.8.3 SPI Control Programming
        4. 9.4.8.4 Watchdog Timing
    5. 9.5 Programming
      1. 9.5.1 SPI Communication
        1. 9.5.1.1 Chip Select Not (nCS)
        2. 9.5.1.2 Serial Clock Input (CLK)
        3. 9.5.1.3 Serial Data Input (SDI)
        4. 9.5.1.4 Serial Data Output (SDO)
    6. 9.6 Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Normal Mode Application Note
        2. 10.2.1.2 Standby Mode Application Note
        3. 10.2.1.3 TXD Dominant State Timeout Application Note
      2. 10.2.2 Detailed Design Procedures
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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订购信息

7.7 Electrical Characteristics

over operating TA temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RXD OUTPUT TERMINAL (OPEN DRAIN)
VOL Output low voltage Based upon a 2 kΩ to 10 kΩ external pull-up to VCC 0.2 VCC
IOL Low level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA
ILKG Leakage current, high-level LIN = VSUP, RXD = VCC –5 0 5 µA
TXD INPUT TERMINAL
VIL Low level input voltage –0.3 0.8 V
VIH High level input voltage 2 5.5 V
IIH High level input leakage current TXD = high –5 0 5 µA
RTXD Internal pull-up resistor value 125 350 800 kΩ
LIN TERMINAL (REFERENCED TO VSUP)
VOH HIGH level output voltage LIN recessive, TXD = high, IO = 0 mA, VSUP = 5.5 V to 36 V 0.85 VSUP
VOL LOW level output voltage LIN dominant, TXD = low, VSUP = 5.5 V to 36 V 0.2 VSUP
VSUP_NON_OP VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) TXD & RXD open VLIN = 5.5 V to 45 V –0.3 45 V
IBUS_LIM Limiting current (ISO/DIS 17987 Param 12) TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω, VSUP = 36 V,
VBUSdom < 4.518 V; Figure 8-6		 40 90 200 mA
IBUS_PAS_dom Receiver leakage current, dominant (ISO/DIS 17987 Param 13) VLIN = 0 V, VSUP = 12 V Driver off/recessive; Figure 8-7 –1 mA
IBUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 36 V Driver off; Figure 8-8 20 µA
IBUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) VLIN = VSUP, Driver off; Figure 8-8 –5 5 µA
IBUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15) GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤ 28 V; Figure 8-9 –1 1 mA
IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS 17987 Param 16) 0 V ≤ VLIN ≤ 28 V, VSUP = GND; Figure 8-10 10 µA
VBUSdom Low level input voltage (ISO/DIS 17987 Param 17) LIN dominant (including LIN dominant for wake up); Figure 8-3, Figure 8-4 0.4 VSUP
VBUSrec High level input voltage (ISO/DIS 17987 Param 18) LIN recessive; Figure 8-3, Figure 8-8 0.6 VSUP
VBUS_CNT Receiver center threshold (ISO/DIS 17987 Param 19) VBUS_CNT = (VIL + VIH)/2; Figure 8-3, Figure 8-8 0.475 0.5 0.525 VSUP
VHYS Hysteresis voltage (ISO/DIS 17987 Param 20) VHYS = (VIL - VIH); Figure 8-3, Figure 8-8 0.175 VSUP
VSERIAL_DIODE Serial diode LIN term pull-up path (ISO/DIS 17987 Param 21) By design and characterization 0.4 0.7 1.0 V
RResponder Pull-up resistor to VSUP (ISO/DIS 17987 Param 26) Normal and Standby modes 20 45 60 kΩ
IRSLEEP Pull-up current source to VSUP Sleep mode, VSUP = 12 V, LIN = GND –20 –2 µA
CLIN,PIN Capacitance of the LIN pin By design and characterization 45 pF
EN INPUT TERMINAL
VIH High level input voltage 2 5.5 V
VIL Low level input voltage 0.8 V
VHYS Hysteresis voltage By design and characterization 30 500 mV
IIL Low level input current EN = Low –8 8 µA
REN Internal pull-down resistor 125 350 800 kΩ
LIMP OUTPUT TERMINAL (HIGH VOLTAGE OPEN DRAIN OUTPUT)
ΔVH High level voltage drop LIMP with respect to VSUP ILIMP = - 0.5 mA 0.5 1 V
ILKG(LIMP) Leakage current LIMP = 0 V, Sleep Mode –0.5 0.5 µA
WAKE INPUT TERMINAL
VIH High-level input voltage Selective Wake-up or Standby Mode, WAKE pin enabled VSUP – 2 V
VIL Low-level input voltage Selective Wake-up or Standby Mode, WAKE pin enabled VSUP – 3 V
IIH High-level input leakage current WAKE = VSUP - 1 V –25 –15 µA
IIL Ligh-level input leakage current WAKE = 1 V 15 25 µA
tWAKE WAKE hold time Wake up time from a wake edge on WAKE; Standby or Sleep mode 5 50 µs
WDI, SDI, SCK, nCS INPUT TERMINAL
VIH High-level input voltage 2.19 V
VIL Low-level input voltage 0.8 V
IIH High-level input leakage current Inputs = VCC –1 1 µA
IIL Low-level input leakage current Inputs = 0 V, VCC = Active –50 -5 µA
CIN Input Capacitance 4 MHz 10 15 pF
ILKG(OFF) Unpowered leakage current Inputs = 5.25/3.465 V, VCC = VSUP = 0 V –1 1 µA
WDT INPUT TERMINAL
VIH High-level input voltage Inputs = VCC 0.8 VCC
VIL Low-level input voltage Inputs = VCC 0.2 VCC
VIM(WDT) WDT Mid-level input voltage(1) Inputs = VCC 0.4 0.5 0.6 VCC
IIH High-level input leakage current Inputs = VCC 2.5 25 µA
IIL Low-level input leakage current Inputs = 0 V, VCC = Active –25 –2.5 µA
ILKG(OFF) Unpowered leakage current Inputs = 5.25/3.465 V, VCC = VSUP = 0 V –1 1 µA
SDO OUTPUT TERMINAL
VOH High level output voltage IO = 2 mA, VCC = Active 0.8 VCC
VOL Low level output voltage IO = 2 mA, VCC = Active 0.2 VCC
ILKG(OFF) Unpowered leakage current Outputs = 5.25/3.465 V, VCC = VSUP = 0 V –1 1 µA
nRST, nWDR (SPI Mode) TERMINAL (OPEN DRAIN OUTPUT)
ILKG Leakage current, high-level LIN = VSUP, nRST = VCC –5 5 µA
VOL Low-level output voltage Based upon external pull up to VCC 0.2 VCC
IOL Low-level output current, open drain LIN = 0 V, nRST = 0.4 V 1.5 mA
nINT, nWDR (Pin Mode) TERMINAL (OPEN DRAIN OUTPUT)
VOL Low-level output voltage 0.2 VCC
IOL Low-level output current, open drain LIN = 0 V, nINT = 0.4 V 1.5 mA
ILKG Leakage current, high-level LIN = VSUP, nINT = VCC –5 5 µA
WDI, WDT TIMING and SWITCHING CHARACTERISTIC (RL = 1 MΩ, CL = 50 pF and TA = -40°C to 125°C)
tW WDI pulse width; see Figure 8-19 Filter time to avoid false input 30 µs
td nWDR pulse width delay time that sets the lower window boundry starting point; see Figure 8-19 Time from nWDR low to high 2 4 6 ms
tWINDOW Closed Window + Open Window; See Figure 8-19 WDT = GND 32 40 48 ms
WDT = VCC 480 600 720 ms
WDT = Floating 4.8 6 7.2 s
tWDOUT Watchdog timeout window (Open Window); See Figure 8-19 WDT = GND 16 20 24 ms
WDT = VCC 240 300 360 ms
WDT = Floating 2.4 3 3.6 s
tPHL Propagation delay time high to low level output (VCC to nWDR delay) VCC = Active 40 65 µs
DUTY CYCLE CHARACTERISTICS(2)
D112V Duty Cycle 1 (ISO/DIS 17987 Param 27) THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12)		 0.396
D212V Duty Cycle 2 (ISO/DIS 17987 Param 28) THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP, VSUP = 5.5 V to 18 V,
tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12)		 0.581
D312V Duty Cycle 3 (ISO/DIS 17987 Param 29) THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4 kbps),
D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-11, Figure 8-12)		 0.417
D412V Duty Cycle 4 (ISO/DIS 17987 Param 30) THREC(MIN) = 0.389 x VSUP,
THDOM(MIN) = 0.251 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4 kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-11, Figure 8-12)		 0.59
(1) This is the measured voltage at the WDT pin when left floating. The WDT pin should be connected directly to VCC, GND or left floating.