ZHCSGV2J June 2009 – January 2017 OMAP-L138
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
Registers for the McASP are summarized in Table 6-51. The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-52
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-53. Note that the AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port.
BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION |
---|---|---|
0x01D0 0000 | REV | Revision identification register |
0x01D0 0010 | PFUNC | Pin function register |
0x01D0 0014 | PDIR | Pin direction register |
0x01D0 0018 | PDOUT | Pin data output register |
0x01D0 001C | PDIN | Read returns: Pin data input register |
0x01D0 001C | PDSET | Writes affect: Pin data set register (alternate write address: PDOUT) |
0x01D0 0020 | PDCLR | Pin data clear register (alternate write address: PDOUT) |
0x01D0 0044 | GBLCTL | Global control register |
0x01D0 0048 | AMUTE | Audio mute control register |
0x01D0 004C | DLBCTL | Digital loopback control register |
0x01D0 0050 | DITCTL | DIT mode control register |
0x01D0 0060 | RGBLCTL | Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows receiver to be reset independently from transmitter |
0x01D0 0064 | RMASK | Receive format unit bit mask register |
0x01D0 0068 | RFMT | Receive bit stream format register |
0x01D0 006C | AFSRCTL | Receive frame sync control register |
0x01D0 0070 | ACLKRCTL | Receive clock control register |
0x01D0 0074 | AHCLKRCTL | Receive high-frequency clock control register |
0x01D0 0078 | RTDM | Receive TDM time slot 0-31 register |
0x01D0 007C | RINTCTL | Receiver interrupt control register |
0x01D0 0080 | RSTAT | Receiver status register |
0x01D0 0084 | RSLOT | Current receive TDM time slot register |
0x01D0 0088 | RCLKCHK | Receive clock check control register |
0x01D0 008C | REVTCTL | Receiver DMA event control register |
0x01D0 00A0 | XGBLCTL | Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows transmitter to be reset independently from receiver |
0x01D0 00A4 | XMASK | Transmit format unit bit mask register |
0x01D0 00A8 | XFMT | Transmit bit stream format register |
0x01D0 00AC | AFSXCTL | Transmit frame sync control register |
0x01D0 00B0 | ACLKXCTL | Transmit clock control register |
0x01D0 00B4 | AHCLKXCTL | Transmit high-frequency clock control register |
0x01D0 00B8 | XTDM | Transmit TDM time slot 0-31 register |
0x01D0 00BC | XINTCTL | Transmitter interrupt control register |
0x01D0 00C0 | XSTAT | Transmitter status register |
0x01D0 00C4 | XSLOT | Current transmit TDM time slot register |
0x01D0 00C8 | XCLKCHK | Transmit clock check control register |
0x01D0 00CC | XEVTCTL | Transmitter DMA event control register |
0x01D0 0100 | DITCSRA0 | Left (even TDM time slot) channel status register (DIT mode) 0 |
0x01D0 0104 | DITCSRA1 | Left (even TDM time slot) channel status register (DIT mode) 1 |
0x01D0 0108 | DITCSRA2 | Left (even TDM time slot) channel status register (DIT mode) 2 |
0x01D0 010C | DITCSRA3 | Left (even TDM time slot) channel status register (DIT mode) 3 |
0x01D0 0110 | DITCSRA4 | Left (even TDM time slot) channel status register (DIT mode) 4 |
0x01D0 0114 | DITCSRA5 | Left (even TDM time slot) channel status register (DIT mode) 5 |
0x01D0 0118 | DITCSRB0 | Right (odd TDM time slot) channel status register (DIT mode) 0 |
0x01D0 011C | DITCSRB1 | Right (odd TDM time slot) channel status register (DIT mode) 1 |
0x01D0 0120 | DITCSRB2 | Right (odd TDM time slot) channel status register (DIT mode) 2 |
0x01D0 0124 | DITCSRB3 | Right (odd TDM time slot) channel status register (DIT mode) 3 |
0x01D0 0128 | DITCSRB4 | Right (odd TDM time slot) channel status register (DIT mode) 4 |
0x01D0 012C | DITCSRB5 | Right (odd TDM time slot) channel status register (DIT mode) 5 |
0x01D0 0130 | DITUDRA0 | Left (even TDM time slot) channel user data register (DIT mode) 0 |
0x01D0 0134 | DITUDRA1 | Left (even TDM time slot) channel user data register (DIT mode) 1 |
0x01D0 0138 | DITUDRA2 | Left (even TDM time slot) channel user data register (DIT mode) 2 |
0x01D0 013C | DITUDRA3 | Left (even TDM time slot) channel user data register (DIT mode) 3 |
0x01D0 0140 | DITUDRA4 | Left (even TDM time slot) channel user data register (DIT mode) 4 |
0x01D0 0144 | DITUDRA5 | Left (even TDM time slot) channel user data register (DIT mode) 5 |
0x01D0 0148 | DITUDRB0 | Right (odd TDM time slot) channel user data register (DIT mode) 0 |
0x01D0 014C | DITUDRB1 | Right (odd TDM time slot) channel user data register (DIT mode) 1 |
0x01D0 0150 | DITUDRB2 | Right (odd TDM time slot) channel user data register (DIT mode) 2 |
0x01D0 0154 | DITUDRB3 | Right (odd TDM time slot) channel user data register (DIT mode) 3 |
0x01D0 0158 | DITUDRB4 | Right (odd TDM time slot) channel user data register (DIT mode) 4 |
0x01D0 015C | DITUDRB5 | Right (odd TDM time slot) channel user data register (DIT mode) 5 |
0x01D0 0180 | SRCTL0 | Serializer control register 0 |
0x01D0 0184 | SRCTL1 | Serializer control register 1 |
0x01D0 0188 | SRCTL2 | Serializer control register 2 |
0x01D0 018C | SRCTL3 | Serializer control register 3 |
0x01D0 0190 | SRCTL4 | Serializer control register 4 |
0x01D0 0194 | SRCTL5 | Serializer control register 5 |
0x01D0 0198 | SRCTL6 | Serializer control register 6 |
0x01D0 019C | SRCTL7 | Serializer control register 7 |
0x01D0 01A0 | SRCTL8 | Serializer control register 8 |
0x01D0 01A4 | SRCTL9 | Serializer control register 9 |
0x01D0 01A8 | SRCTL10 | Serializer control register 10 |
0x01D0 01AC | SRCTL11 | Serializer control register 11 |
0x01D0 01B0 | SRCTL12 | Serializer control register 12 |
0x01D0 01B4 | SRCTL13 | Serializer control register 13 |
0x01D0 01B8 | SRCTL14 | Serializer control register 14 |
0x01D0 01BC | SRCTL15 | Serializer control register 15 |
0x01D0 0200 | XBUF0(1) | Transmit buffer register for serializer 0 |
0x01D0 0204 | XBUF1(1) | Transmit buffer register for serializer 1 |
0x01D0 0208 | XBUF2(1) | Transmit buffer register for serializer 2 |
0x01D0 020C | XBUF3(1) | Transmit buffer register for serializer 3 |
0x01D0 0210 | XBUF4(1) | Transmit buffer register for serializer 4 |
0x01D0 0214 | XBUF5(1) | Transmit buffer register for serializer 5 |
0x01D0 0218 | XBUF6(1) | Transmit buffer register for serializer 6 |
0x01D0 021C | XBUF7(1) | Transmit buffer register for serializer 7 |
0x01D0 0220 | XBUF8(1) | Transmit buffer register for serializer 8 |
0x01D0 0224 | XBUF9(1) | Transmit buffer register for serializer 9 |
0x01D0 0228 | XBUF10(1) | Transmit buffer register for serializer 10 |
0x01D0 022C | XBUF11(1) | Transmit buffer register for serializer 11 |
0x01D0 0230 | XBUF12(1) | Transmit buffer register for serializer 12 |
0x01D0 0234 | XBUF13(1) | Transmit buffer register for serializer 13 |
0x01D0 0238 | XBUF14(1) | Transmit buffer register for serializer 14 |
0x01D0 023C | XBUF15(1) | Transmit buffer register for serializer 15 |
0x01D0 0280 | RBUF0(2) | Receive buffer register for serializer 0 |
0x01D0 0284 | RBUF1(2) | Receive buffer register for serializer 1 |
0x01D0 0288 | RBUF2(2) | Receive buffer register for serializer 2 |
0x01D0 028C | RBUF3(2) | Receive buffer register for serializer 3 |
0x01D0 0290 | RBUF4(2) | Receive buffer register for serializer 4 |
0x01D0 0294 | RBUF5(2) | Receive buffer register for serializer 5 |
0x01D0 0298 | RBUF6(2) | Receive buffer register for serializer 6 |
0x01D0 029C | RBUF7(2) | Receive buffer register for serializer 7 |
0x01D0 02A0 | RBUF8(2) | Receive buffer register for serializer 8 |
0x01D0 02A4 | RBUF9(2) | Receive buffer register for serializer 9 |
0x01D0 02A8 | RBUF10(2) | Receive buffer register for serializer 10 |
0x01D0 02AC | RBUF11(2) | Receive buffer register for serializer 11 |
0x01D0 02B0 | RBUF12(2) | Receive buffer register for serializer 12 |
0x01D0 02B4 | RBUF13(2) | Receive buffer register for serializer 13 |
0x01D0 02B8 | RBUF14(2) | Receive buffer register for serializer 14 |
0x01D0 02BC | RBUF15(2) | Receive buffer register for serializer 15 |
ACCESS TYPE | BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION |
---|---|---|---|
Read Accesses | 0x01D0 2000 | RBUF | Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Reads from DMA port only if XBUSEL = 0 in XFMT. |
Write Accesses | 0x01D0 2000 | XBUF | Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if RBUSEL = 0 in RFMT. |
BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION |
---|---|---|
0x01D0 1000 | AFIFOREV | AFIFO revision identification register |
0x01D0 1010 | WFIFOCTL | Write FIFO control register |
0x01D0 1014 | WFIFOSTS | Write FIFO status register |
0x01D0 1018 | RFIFOCTL | Read FIFO control register |
0x01D0 101C | RFIFOSTS | Read FIFO status register |