8.2.1.2.8 Control Loop Compensation

The LM2743 uses voltage-mode (‘VM’) PWM control to correct changes in output voltage due to line and load transients. One of the attractive advantages of voltage mode control is its relative immunity to noise and layout. However VM requires careful small signal compensation of the control loop for achieving high bandwidth and good phase margin.

The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the LM2743 is a 9-MHz op-amp used in the classic inverting configuration. Figure 32 shows the regulator and control loop components.

Figure 32. Power Stage and Error Amplifier

One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to see. Software tools such as Excel, MathCAD, and Matlab are useful for showing how changes in compensation or the power stage affect system gain and phase.

The power stage modulator provides a DC gain A_DC that is equal to the input voltage divided by the peak-to-peak value of the PWM ramp. This ramp is 1.0VP-P for the LM2743. The inductor and output capacitor create a double pole at frequency f_DP, and the capacitor ESR and capacitance create a single zero at frequency f_ESR. For this example, with V_IN = 3.3 V, these quantities are:

Equation 30.

Equation 31.

Equation 32.

In the equation for f_DP, the variable R_L is the power stage resistance, and represents the inductor DCR plus the on resistance of the top power MOSFET. R_O is the output voltage divided by output current. The power stage transfer function G_PS is given by the following equation, and Figure 34 shows Bode plots of the phase and gain in this example.

Equation 33.

where

• a = LC_O(R_O + R_C)
• b = L + C_O(R_OR_L + R_OR_C + R_CR_L)
• c = R_O + R_L

Figure 33. Gain vs Frequency

Figure 34. Power Stage Gain and Phase

The double pole at 4.5 kHz causes the phase to drop to approximately -130° at around 10 kHz. The ESR zero, at 20.3 kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left uncompensated, the bandwidth would be approximately 10 kHz and the phase margin 53°. In theory, the loop would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is compensated using the error amplifier and a few passive components.

For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.

In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC gain as high as possible. Two zeroes f_Z1 and f_Z2 are placed at the double pole frequency to cancel the double pole phase lag. Then, a pole, f_P1 is placed at the frequency of the ESR zero. A final pole f_P2 is placed at one-half of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the switching frequency, or 60 kHz for this example. The generic equation for the error amplifier transfer function is:

Equation 34.

In this equation, the variable A_EA is a ratio of the values of the capacitance and resistance of the compensation components, arranged as shown in Figure 32. A_EA is selected to provide the desired bandwidth. A starting value of 80,000 for A_EA should give a conservative bandwidth. Increasing the value will increase the bandwidth, but will also decrease phase margin. Designs with 45° to 60° are usually best because they represent a good trade-off between bandwidth and phase margin. In general, phase margin is lowest and gain highest (worst-case) for maximum input voltage and minimum output current. One method to select A_EA is to use an iterative process beginning with these worst-case conditions.

1. Increase A_EA
2. Check overall bandwidth and phase margin
3. Change V_IN to minimum and recheck overall bandwidth and phase margin
4. Change I_O to maximum and recheck overall bandwidth and phase margin

The process ends when the both bandwidth and the phase margin are sufficiently high. For this example input voltage can vary from 3.0 to 3.6 V and output current can vary from 0 to 4 A, and after a few iterations a moderate gain factor of 101 dB is used.

The error amplifier of the LM2743 has a unity-gain bandwidth of 9 MHz. In order to model the effect of this limitation, the open-loop gain can be calculated as:

Equation 35.

The new error amplifier transfer function that takes into account unity-gain bandwidth is:

Equation 36.

The gain and phase of the error amplifier are shown in Figure 36.

Figure 35. Gain vs Frequency

Figure 36. Error Amplifier Gain and Phase

In VM regulators, the top feedback resistor R_FB2 forms a part of the compensation. Setting R_FB2 to 10 kΩ, ±1% usually gives values for the other compensation resistors and capacitors that fall within a reasonable range. (Capacitances > 1 pF, resistances < 1 MΩ) C_C1, C_C2, C_C3, R_C1, and R_C2 are selected to provide the poles and zeroes at the desired frequencies, using the following equations:

Equation 37.

Equation 38.

Equation 39.

Equation 40.

Equation 41.

In practice, a good trade off between phase margin and bandwidth can be obtained by selecting the closest ±10% capacitor values above what are suggested for C_C1 and C_C2, the closest ±10% capacitor value below the suggestion for C_C3, and the closest ±1% resistor values below the suggestions for R_C1, R_C2. Note that if the suggested value for R_C2 is less than 100Ω, it should be replaced by a short circuit. Following this guideline, the compensation components will be:

 C_C1 = 27 pF ±10%

 C_C2 = 820 pF ±10%

 C_C3 = 2.7 nF ±10%

 R_C1 = 39.2 kΩ ±1%

 R_C2 = 2.55 kΩ ±1%

The transfer function of the compensation block can be derived by considering the compensation components as impedance blocks Z_F and Z_I around an inverting op-amp:

Equation 42.

Equation 43.

Equation 44.

As with the generic equation, G_EA-ACTUAL must be modified to take into account the limited bandwidth of the error amplifier. The result is:

Equation 45.

The total control loop transfer function H is equal to the power stage transfer function multiplied by the error amplifier transfer function.

The bandwidth and phase margin can be read graphically from Bode plots of H_EA are shown in Figure 38.

Figure 37. Gain vs Frequency

Figure 38. Overall Loop Gain and Phase

The bandwidth of this example circuit is 59 kHz, with a phase margin of 60°.