ZHCSLX3C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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Pin Functions

PINI/ODESCRIPTION
NAMENO.
CAPL32OConnect a single 2.2-µF capacitor to GND.
CTRL123I/O

Host-side control interface. These pins are used to implement I2C or SPI depending on the PROTOCOL_SEL pin configuration.

I2C mode (PROTOCOL_SEL = Float or High):

CTRL1: SCL – I2C Clock input / open-drain output

CTRL2: SDA – I2C Data input / open-drain output

CTRL3: SET_ADDR_N – input, address assignment enable. Also used to receive external LED clock.

CTRL4: ADDR_DONE_N – output, address assignment complete. Also used to transmit LED clock.

SPI mode (PROTOCOL_SEL = GND):

CTRL1: SCK – Serial clock input

CTRL2: SS_N – Active-low slave select input

CTRL3: MOSI – Master output or slave input

CTRL4: MISO – Master input or slave output

CTRL224I/O
CTRL328I, Weak internal pullup
CTRL421O
EN22I, Weak internal pullupDevice enable. When EN = 0, the FPC402 is in a power-down state and does not respond to the host-side control bus, nor does it perform port-side I2C accesses. When EN=VDD2 or Float, the FPC402 is fully enabled and will respond to the host-side control bus provided VDD1 and VDD2 power has been stable for at least TPOR. VIH for this pin is referenced to VDD2.

The minimum required assert and deassert time is 12.5 µs.

GPIO[0]42I/OGeneral-purpose I/O. Output high voltage (VOH) and input high voltage (VIH) are based on VDD1. Configured as input (high-Z) by default.
GPIO[1]53
GPIO[2]8
GPIO[3]19
GND27, DAPPowerGround reference. The GND pins must be connected through a low-resistance path to the board GND plane.
HOST_INT_N25O, Open-DrainOpen-drain 3.3-V tolerant active-low interrupt output. It asserts low to interrupt the host. The events which trigger an interrupt are programmable through registers. This pin can be connected in a wired-OR fashion with other FPC402s’ interrupt pins. A single pullup resistor to VDD1 or VDD2 in the 2-kΩ to 5-kΩ range is adequate for the entire net.
IN_A[0]41I, Weak internal pullup

Low-speed port status input A.

Example usage:

SFP: Mod_ABS[3:0]

QSFP: ModPrsL[3:0]

IN_A[1]50
IN_A[2]55
IN_A[3]10
IN_B[0]39I, Weak internal pullup

Low-speed port status input B.

Example usage:

SFP: Tx_Fault[3:0]

QSFP: IntL[3:0]

IN_B[1]47
IN_B[2]1
IN_B[3]12
IN_C[0]37I, Weak internal pullup

Low-speed port status input C.

Example usage:

SFP: Rx_LOS[3:0]

QSFP: N/A

IN_C[1]46
IN_C[2]3
IN_C[3]14
MOD_SCL[0]36I/O, Open-DrainI2C clock open-drain output to the module. External 2-kΩ to 5-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant.
MOD_SCL[1]49
MOD_SCL[2]4
MOD_SCL[3]15
MOD_SDA[0]35I/O, Open-DrainI2C data input or open-drain output to the module. External 2-kΩ to 5-kΩ pullup resistor is required. This pin is 3.3-V LVCMOS tolerant.
MOD_SDA[1]48
MOD_SDA[2]5
MOD_SDA[3]16
OUT_A[0]40O

Low-speed port control output A. OUT_A is disabled by default (high-Z) and when enabled drives high logic unless reprogrammed. A 10-kΩ pullup or pulldown resistor is recommended to set a default logic value before this output is enabled. See Section 8.3.3 for more details.

Example usage:

SFP: Tx_Disable[3:0]

QSFP: ResetL[3:0]

OUT_A[1]44
OUT_A[2]56
OUT_A[3]11
OUT_B[0]38O

Low-speed port control output B. Output is disabled by default (high-Z) and when enabled drives low logic unless reprogrammed. A 10-kΩ pullup or pulldown resistor is recommended to set a default logic value before this output is enabled. See Section 8.3.3 for more details.

Example usage:

SFP: RS[3:0]

QSFP: LPMode[3:0]

OUT_B[1]45
OUT_B[2]2
OUT_B[3]13
OUT_C[0]34O

Low-speed port control output C. Can be used to drive port status LED. Special LED driving features are available on this output. This output is enabled and high logic by default at power up. See Section 8.3.2 for more details.

Example usage:

SFP: LED_GRN[3:0]

QSFP: LED_GRN[3:0]

This pin requires a series resistor with a value of at least 33 Ω. The LED current-limiting resistor can serve for this purpose.

OUT_C[1]51
OUT_C[2]6
OUT_C[3]17
OUT_D[0]33O

Low-speed port control output D. Can be used to drive port status LED. Special LED driving features are available on this output. This output is enabled and high logic by default at power up. See Section 8.3.2 for more details.

Example usage:

SFP: LED_YLW[3:0]

QSFP: N/A

This pin requires a series resistor with a value of at least 33 Ω. The LED current-limiting resistor can serve for this purpose.

OUT_D[1]52
OUT_D[2]7
OUT_D[3]18
PROTOCOL_SEL31I, Weak internal pullupUsed to select between I2C and SPI host-side control interface.
Float or High: Inter-IC Control (I2C)
GND: Serial Peripheral Interface (SPI)
SPI_LED_SYNC30I/O

LED clock synchronization pin for SPI mode only.

When using SPI as the host-side control interface (PROTOCOL_SEL=GND), connect all FPC402 SPI_LED_CLK pins together. This ensures LED synchronization across all FPC402 devices.

When using I2C as the host-side control interface, this pin can be floating. LED synchronization is ensured by other means in I2C mode.

TEST_N29I, Weak internal pullupTI test mode.
Float or High: Normal operation
GND: TI Test Mode
VDD19, 43, 54PowerMain power supply, VDD1 = 3.3 V ± 5%. TI recommends connecting at least one 1-µF and one 0.1-µF decoupling capacitors per VDD1 pin as close to the pin as possible.
VDD220, 26PowerPower supply for host-side interface I/Os (CTRL[4:1]). VDD2 can be 1.8 V to 3.3 V ± 5%. If the host-side interface operates at 3.3 V, then VDD1 and VDD2 can be connected to the same 3.3-V ± 5% supply. TI recommends connecting at least one 1-µF and one 0.1-µF decoupling capacitors per VDD2 pin as close to the pin as possible.