ZHCSLX3C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.3.4 Low-Speed Input Status and Interrupt Generation

The FPC402 has three general-purpose inputs per port which can be used to monitor the low-speed outputs from the module. The host controller can monitor the status of these signals for each port by reading the appropriate registers in the FPC402. In addition, the FPC402 can be configured to generate an interrupt to the host through the HOST_INT_N signal whenever one or more of the low-speed input signals change state. The interrupt can be configured to trigger on the falling edge, the rising edge, or both the falling and rising edges. A single register stores flags for which inputs and edges are responsible for the trigger.

The recommended signal connection is as follows. IN_A, IN_B, and IN_C are not restricted to this port pin assignment, and in fact they can be used to monitor the status of any low-speed 3.3-V signal required for the application.

Table 8-2 Example Connections for Low-Speed FPC402 Inputs to SFP/QSFP ports
PIN NAMEEXAMPLE CONNECTIONCOMMENT
SFPQSFP
IN_ATx_FaultIntL
IN_BMod_ABSModPrsL
IN_CRx_LOS—This pin is unused in QSFP applications, or it can be utilized as a general-purpose input.

The events which trigger an active-low interrupt on the HOST_INT_N pin are user-configurable. The HOST_INT_N pins from multiple FPC402 devices can be connected together in a wired-or fashion. Interrupt generation can be configured as follows:

Table 8-3 Host-Side Interrupt Options
INTERRUPT-TRIGGERING EVENTPIN(S) MONITOREDEXAMPLE APPLICATION(1)
Rising edgeIN_AIndicates deassertion of port-side interrupt (Tx_Fault or IntL).
IN_BIndicates that a module has been removed.
IN_CIndicates loss of optical signal (Rx_LOS) for SFP applications.
IN_A, IN_B, or IN_CIndicates deassertion of port-side interrupt, removal of module, or loss of optical signal (Rx_LOS).
Falling edgeIN_AIndicates assertion of port-side interrupt (Tx_Fault or IntL).
IN_BIndicates that a module has been inserted.
IN_CIndicates presence of optical signal (Rx_LOS) for SFP applications.
IN_A, IN_B, or IN_CIndicates assertion of port-side interrupt, insertion of module, or presence of optical signal (Rx_LOS).
Rising or falling edgeIN_AIndicates assertion or deassertion of port-side interrupt (Tx_Fault or IntL).
IN_BIndicates that a module has been inserted/removed.
IN_CIndicates presence or absence of optical signal (Rx_LOS) for SFP applications.
IN_A, IN_B, or IN_CIndicates assertion or deassertion of port-side interrupt, the insertion or removal of module, or the presence or absence of optical signal (Rx_LOS).
(1) Example applications assume that IN_A, IN_B, and IN_C are connected to the downstream ports as per the example connection table, Table 8-2.

The FPC402 is also able to generate an interrupt based on prefetched data. This is known as a data-driven interrupt. The FPC402 monitors up to four bytes within the prefetched range for each port. For each of the bytes, the register offset address is programmed to a local FPC402 register as well as the enable bit fields which will trigger the interrupt. When one of the enabled bits of the four monitored bytes changes state from a 0 to a 1 and stays a 1 for two consecutive periodic prefetch cycles (0→1→1), the interrupt is generated and the periodic prefetch operation is halted. The FPC402 has four port-specific registers which contain the sampled data from the bytes being monitored after the interrupt is triggered. To clear the interrupt, the sampled data register of the trigger source byte is read. The periodic prefetch must be restarted after the interrupt is cleared with an I2C command. Because it takes two periodic prefetch cycles to trigger this interrupt, it may take up to 10 ms for the host to see the trigger after the monitored bit field of the downstream module changes for the fastest periodic prefetch setting.

The FPC402 also has the ability to generate an interrupt if there is a mishap in the downstream I2C bus. The SDA bus and the SCL bus each have timers that will trigger an interrupt if they are held in a low state too long due to excessive clock stretching or a port error. Once the interrupt is triggered, it is cleared by issuing a port reset on the relevant port. These interrupts are known as SCL Stuck and SDA Stuck interrupts and can be configured individually for each port. By default, the SCL Stuck interrupt will trigger after the SCL bus is held low for 35 ms (typical). This value is configurable individually by port. The SDA Stuck interrupt will trigger after the SDA is held low for 1 s (typical). The user may issue a port reset sequence (9 consecutive SCL clock cycles with the last being an I2C stop condition) or module reset to restore the module to a known state.

When a host-side interrupt is triggered, the host must determine the source and cause of the interrupt. The recommended procedure for identifying the source and cause of an interrupt is as follows:

  1. Read the FPC402 aggregated port interrupt flags of the first FPC402 instance to see which, if any, downstream port triggered the interrupt.
  2. If this instance of the FPC402 has any aggregated port interrupts flagged, read all of the status registers to determine the source of the interrupt and clear it. If an SCL Stuck or SDA Stuck interrupt is triggered, a port reset must be issued and the periodic prefetch must be restarted. The host may also perform other housekeeping activities based on the interrupt, such as change the state of the LEDs after a module is no longer present.
  3. Repeat steps 1 and 2 for the next FPC402 instance, until the HOST_INT_N bus is cleared.

This procedure applies to every FPC402 device which is wire-or’ed to the host-side interrupt signal. The total time required for the host to identify the source and cause of the interrupt for an implementation consisting of N total FPC402s, where all N HOST_INT_N outputs are wire-or’ed together, is as follows:

Tinterrupt = Delay between the IN_* pin changing state and the corresponding FPC402 device triggering an interrupt (50 µs maximum).

Tread = Time required to read a single register from N FPC402 devices.

For I2C mode, Tread = (9 × 4 × N)/FI2C, where FI2C is the SCL clock frequency.

For SPI mode, Tread = (29 × 2 × N)/FSPI + TOFF-SSN, where FSPI is the SCK clock frequency, and TOFF-SSN is the SS_N off time.

Ttotal = Tinterrupt + 4 × Tread

Table 8-4 gives some examples of Ttotal for different I2C/SPI frequencies and different values of N.

Table 8-4 Example Calculations for Determining the Source and Cause of a Host-Side Interrupt
MODEFI2CFSPINTread (ms)Ttotal (ms)
I2C100 kHz–10.361.5
I2C100 kHz–41.445.8
I2C100 kHz–82.8811.6
I2C100 kHz–124.3217.3
I2C400 kHz–10.090.4
I2C400 kHz–40.361.5
I2C400 kHz–80.722.9
I2C400 kHz–121.084.4
I2C1000 kHz–10.00360.1
I2C1000 kHz–40.1440.6
I2C1000 kHz–80.2881.2
I2C1000 kHz–120.4321.8
SPI–1 MHz10.060.3
SPI–1 MHz40.231.0
SPI–1 MHz80.471.9
SPI–1 MHz120.702.8
SPI–10 MHz10.010.1
SPI–10 MHz40.020.1
SPI–10 MHz80.050.2
SPI–10 MHz120.070.3

Click here to request access to the FPC401 Programmer's Guide (SNLU221) for more details on how to configure the interrupts.