ZHCSLX3C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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9.2.1 SFP/QSFP Port Management

The FPC402 can be used to manage the low-speed signals, I2C, and LEDs for multiple SFP and/or QSFP ports, up to four per FPC402 device. The FPC402 package is optimized to allow placement underneath an SFP or QSFP port on the opposite side of the board. This allows hardware designers to terminate all SFP/QSFP low-speed signals close to the port and route a single I2C or SPI interface back to the system controller (ASIC or FPGA). Figure 9-2 shows an example of this application where two FPC402 devices are used to control two QSFP ports and six SFP ports, in addition to controlling LEDs and two TPS2556 power distribution switches. Figure 9-3 shows an example schematic for the first four ports of this application.

GUID-A832038B-F3E8-474C-AF9C-C64B3561D23B-low.gifFigure 9-2 SFP/QSFP Application Block Diagram
GUID-4B4FEDCF-2590-4DEC-AD6E-9F94AF34F2B3-low.gifFigure 9-3 SFP/QSFP Application Schematic