ZHCSLX3C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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Low-Speed Output Signal Control

The FPC402 has two general-purpose outputs per port which can be used to drive the low-speed inputs to the module. The host controller can change the state of these outputs for each port individually, for all ports connected to a given FPC402 device simultaneously, or for all ports in the system simultaneously.

There are two configuration registers for these outputs. One register configures the enable state of the OUT_A and OUT_B pins for every port, and by default both OUT_A and OUT_B pins are disabled (tri-stated). The second register controls the output value for all OUT_A and OUT_B pins, where OUT_A has default value of 1 and OUT_B has a default value of 0. The output values must be configured before the outputs are enabled. If a default value is desired during boot up before these pins are enabled, a 10-kΩ pullup or pulldown resistor is recommended (note that SFP and QSFP modules have internal pullup and pulldowns on certain inputs). Note that if the VDD1 rail does not have power and there is an externally powered pullup resistor connected to an output pin, the output pin will be pulled low until VDD1 is supplied.

Table 8-1 provides an example signal connection. OUT_A and OUT_B are not restricted to this port pin assignment, and they can be used to drive any 3.3-V signal required for the application, provided the IOH and IOL limits are met.

Table 8-1 Example Connections for Low-Speed FPC402 Outputs to SFP/QSFP ports
PIN NAMEEXAMPLE CONNECTIONCOMMENT
SFPQSFP
OUT_ATx_DisableResetL
OUT_BRS0 and RS1LPModeRS0 and RS1 will both be driven to the same level.