Reading data from an FPC402 device requires two complete SPI transactions as shown in Figure 8-10. In between these two transactions, the FPC402 fetches the requested information from either the local FPC402 registers or from the downstream port, depending on the address specified in the read transaction. Note that for downstream (also known as remote) register reads, the required time delay between the two transactions is longer:

• Local FPC402 register reads: t_OFF-SSN ≥ 1 µs
• Downstream (remote) register reads: t_OFF-SSN ≥ 170 µs assuming 400-kHz I2C; 620 µs assuming 100-kHz I2C

Also note that the second SPI transaction does not have to be a valid read or write operation and can instead be a dummy frame composed of all ones. This dummy frame is considered an invalid address by the FPC402 so it does not take any actions, but the read data from the prior frame still is shifted out and is valid. The use of a dummy frame is recommended when reading a single local FPC402 register because, if a register is read twice using the same SPI frame, any self-clearing bits will be cleared in the second frame and the received data may be incorrect.

Figure 8-10 SPI Read Consisting of Two Separate SPI Transactions

For downstream (remote) register reads, where the FPC402 must translate a SPI read into an I2C read transaction with the downstream port, the most significant bit of the data returned on MISO indicates whether the downstream port is busy or not. If the second SPI read transaction is executed prematurely during a downstream (remote) read, the returned data will indicated BUSY = 1. When reading from a downstream port at an address that is not prefetched into local FPC402 memory, the time in between the first SPI transaction on a port, where the read is initiated, and the second SPI transaction on the same port, where the data is returned, must be at least 170 µs for a downstream I2C rate of 400 kHz and 620 µs for a downstream I2C rate of 100 kHz. Figure 8-11 shows what happens when this prescribed delay is not followed.

If a back-to-back read transaction is issued to the same downstream port before the FPC402 has completed the first read transaction, then the subsequent transaction will contain status from the second read transaction with REJECT=1, which means that the second transaction was rejected due to the downstream I2C master being busy executing the first read transaction. Figure 8-11 shows what happens when back-to-back reads are issued to the same downstream port without allowing enough time to complete the first read.

Figure 8-11 Back-to-Back SPI Reads From Same Port