ZHCSLX3C June   2017  – September 2020 FPC402

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Host-Side Control Interface
      2. 8.3.2  LED Control
      3. 8.3.3  Low-Speed Output Signal Control
      4. 8.3.4  Low-Speed Input Status and Interrupt Generation
      5. 8.3.5  Downstream (Port-Side) I2C Master
      6. 8.3.6  Data Prefetch From Modules
      7. 8.3.7  Scheduled Write
      8. 8.3.8  Protocol Timeouts
      9. 8.3.9  General-Purpose Inputs and Outputs
      10. 8.3.10 Hot-Plug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 I2C Host-Side Control Interface
      2. 8.4.2 SPI Host-Side Control Interface
        1. 8.4.2.1 SPI Frame Structure
        2. 8.4.2.2 SPI Read Operation
        3. 8.4.2.3 SPI Write Operation
    5. 8.5 Programming
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 SFP/QSFP Port Management
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Recommended Package Footprint
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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Protocol Timeouts

The FPC402 has a watchdog timer to ensure that the I2C buses do not become permanently stuck. For example, if the host is performing a remote access on a downstream module, the FPC402 will clock stretch the host-side I2C while the downstream I2C transaction occurs. If the downstream module clock stretches for a very long time or any other error occurs that prevents the transaction from finishing, the host-side I2C will not become stuck. The watchdog timer is what prevents this from happening by setting a maximum time for the downstream transaction to complete; and if it does not complete, the timer expires and the FPC402 will NACK the host to terminate the transaction. By default, the timer is set to 3 ms and is programmable in steps of 1 ms up to 127 ms. This timer may also be disabled, but this is not recommended as the I2C bus may become permanently stuck and a device reset will be necessary. Each port's I2C master also has a programmable watchdog timer which operates similarly to the host-side I2C watchdog timer.

When the host attempts a remote access transaction through I2C, after the I2C device ID has been ACKed, the FPC402 waits for the host to send a register offset address or a read/write command before downplaying it on the downstream port I2C. If the host becomes busy with something else and does not finish the I2C transaction, the FPC402 state machine will be stuck. There is a protocol timeout timer for each port to prevent this from happening. If the host does not finish the I2C transaction within this timer, the FPC402 will timeout and return to the idle state. This counter is 10 ms (typical) by default and is configurable in steps of 1 ms up to 255 ms.

Click here to request access to the FPC401 Programmer's Guide (SNLU221) for more details on how to configure protocol timeouts.