ZHCSUH8B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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SPI Read Operation

Reading data from an FPC202 device requires two complete SPI transactions as shown in Figure 7-10. In between these two transactions, the FPC202 fetches the requested information from either the local FPC202 registers or from the downstream port, depending on the address specified in the read transaction. Note that for downstream (also known as remote) register reads, the required time delay between the two transactions is longer:

  • Local FPC202 register reads: tOFF-SSN ≥ 1 µs
  • Downstream (remote) register reads: tOFF-SSN ≥ 170 µs assuming 400 kHz I2C; 620 µs assuming 100 kHz I2C

Also note that the second SPI transaction does not have to be a valid read or write operation and can instead be a dummy frame composed of all ones. This dummy frame is considered an invalid address by the FPC202 so it does not take any actions, but the read data from the prior frame still is shifted out and is valid. The use of a dummy frame is recommended when reading a single local FPC202 register because if a register is read twice using the same SPI frame, any self-clearing bits will be cleared in the second frame and the received data may be incorrect.

GUID-57225F71-7774-4B6B-AB13-25BF1D771841-low.gifFigure 7-10 SPI Read Consisting of Two Separate SPI Transactions

For downstream (remote) register reads, where the FPC202 must translate a SPI read into an I2C read transaction with the downstream port, the most significant bit of the data returned on MISO indicates whether the downstream port is busy or not. If the second SPI read transaction is executed prematurely during a downstream (remote) read, the returned data will indicated BUSY = 1. When reading from a downstream port at an address that is not pre-fetched into local FPC202 memory, the time in between the first SPI transaction on a port, where the read is initiated, and the second SPI transaction on the same port, where the data is returned, must be at least 170 µs for a downstream I2C rate of 400 kHz and 620 µs for a downstream I2C rate of 100 kHz. Figure 7-11 shows what happens when this prescribed delay is not followed.

If a back-to-back read transaction is issued to the same downstream port before the FPC202 has completed the first read transaction, then the subsequent transaction will contain status from the second read transaction with REJECT=1, which means that the second transaction was rejected due to the downstream I2C master being busy executing the first read transaction. Figure 7-11 shows what happens when back-to-back reads are issued to the same downstream port without allowing enough time to complete the first read.

GUID-7DAD22F0-BD01-4E16-BC87-534282BB4135-low.gifFigure 7-11 Back-to-Back SPI Reads From Same Port