ZHCSUH8B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.4.2.1 SPI Frame Structure

Each SPI transaction to a single FPC202 device is 29 bits long and is framed by the assertion of SS_N (CTRL2) low. The MOSI (CTRL3) input is ignored and the MISO (CTRL4) output is high impedance whenever SS_N is de-asserted high. The prior SPI command, address, and data are shifted out on MISO as the current SPI command, address, and data are shifted in on MOSI. In all SPI transactions, the MISO output signal is enabled asynchronously whenever SS_N is asserted low.

Table 7-8 shows the structure of a SPI frame. Figure 7-7 shows an example implementation, including the internal SPI registers, for two FPC202 devices.

Table 7-8 SPI Frame Structure
BIT FIELD DESCRIPTION
28 R/W

0: Write command

1: Read command

This is the first bit shifted in on the MOSI input.
27:16 ADDR[11:0] 12-bit address field. See Table 7-7.
15 DATA[15] Busy flag. For read operations, a '1' means the downstream port is busy. For write operations, DATA[15] is a don't care.
14 DATA[14] Don't care.
13 DATA[13] NACK received flag. A '1' means the FPC202 has received a NACK from the downstream port.
12 DATA[12] Reject flag. A '1' means the FPC202 has rejected the previous command because it is busy servicing a prior command.
11:8 DATA[11:8] Don't care.
7:0 DATA[7:0]

8-bit data field.

DATA[0] is the last bit shifted in on the MOSI input.
GUID-FA5C49FB-99C1-4F90-8E3F-1B2194AD533A-low.gifFigure 7-7 Example SPI Implementation For Two FPC202 Devices
GUID-726293DB-6B46-47DB-83DE-DCE1110ABE58-low.gif Figure 7-8 Generic SPI Transaction

The timing specification for an SPI transaction is described in Figure 7-9.

GUID-8E3AA777-C514-4124-A3FB-5AAC86E7D537-low.gif Figure 7-9 SPI Timing Diagram