ZHCSUH8B December   2017  – January 2024 FPC202

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Host-Side Control Interface
      2. 7.3.2  LED Control
        1. 7.3.2.1 Configurations with up to eight LEDs per port
      3. 7.3.3  Low-Speed Output Signal Control
      4. 7.3.4  Low-Speed Input Status and Interrupt Generation
      5. 7.3.5  Downstream (Port-Side) I2C Master
      6. 7.3.6  Data Pre-Fetch From Modules
      7. 7.3.7  Scheduled Write
      8. 7.3.8  Protocol Timeouts
      9. 7.3.9  General-Purpose Inputs/Outputs
      10. 7.3.10 Hot-Plug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Host-Side Control Interface
      2. 7.4.2 SPI Host-Side Control Interface
        1. 7.4.2.1 SPI Frame Structure
        2. 7.4.2.2 SPI Read Operation
        3. 7.4.2.3 SPI Write Operation
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 SFP/QSFP Port Management
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.4 Low-Speed Input Status and Interrupt Generation

The FPC202 has six general-purpose inputs per port which can be used to monitor the low-speed outputs from the module. The host controller can monitor the status of these signals for each port by reading the appropriate registers in the FPC202. In addition, the FPC202 can be configured to generate an interrupt to the host through the HOST_INT_N signal whenever one or more of the low-speed input signals change state. The interrupt can be configured to trigger on the falling edge, the rising edge, or both the falling and rising edges. A single register stores flags for which inputs and edges are responsible for the trigger.

The recommended signal connection is as follows. S0_IN_A, S0_IN_B, S0_IN_C, S1_IN_A, S1_IN_B, and S1_IN_C are not restricted to this port pin assignment, and in fact they can be used to monitor the status of any low-speed 3.3-V signal required for the application.

Table 7-2 Example Connections for Low-Speed FPC202 Inputs to SFP/QSFP ports
PIN NAMEEXAMPLE CONNECTIONCOMMENT
SFPQSFP
S0_IN_ATx_FaultIntL
S0_IN_BMod_ABSModPrsL
S0_IN_CRx_LOS—This pin is unused in QSFP applications, or it can be utilized as a general-purpose input.
S1_IN_AGeneral-purpose input, available for any purpose
S1_IN_BGeneral-purpose input, available for any purpose
S1_IN_CGeneral-purpose input, available for any purpose

The events which trigger an active-low interrupt on the HOST_INT_N pin are user-configurable. Multiple FPC202s’ HOST_INT_N pins can be connected together in a wired-or fashion. Interrupt generation can be configured as follows:

Table 7-3 Host-side interrupt options
INTERRUPT-TRIGGERING EVENTPIN(S) MONITOREDEXAMPLE APPLICATION(1)
Rising edgeS0_IN_AIndicates de-assertion of port-side interrupt (Tx_Fault or IntL).
S0_IN_BIndicates that a module has been removed.
S0_IN_CIndicates loss of optical signal (Rx_LOS) for SFP applications.
S0_IN_A, S0_IN_B, or S0_IN_CIndicates de-assertion of port-side interrupt, removal of module, or loss of optical signal (Rx_LOS).
S1_IN_AIndicates rising edge on S1_IN_A
S1_IN_BIndicates rising edge on S1_IN_B
S1_IN_CIndicates rising edge on S1_IN_C
S1_IN_A, S1_IN_B, or S1_IN_CIndicates rising edge on S1_IN_A, S1_IN_B, or S1_IN_C
Falling edgeS0_IN_AIndicates assertion of port-side interrupt (Tx_Fault or IntL).
S0_IN_BIndicates that a module has been inserted.
S0_IN_CIndicates presence of optical signal (Rx_LOS) for SFP applications.
S0_IN_A, S0_IN_B, or S0_IN_CIndicates assertion of port-side interrupt, insertion of module, or presence of optical signal (Rx_LOS).
S1_IN_AIndicates falling edge on S1_IN_A
S1_IN_BIndicates falling edge on S1_IN_B
S1_IN_CIndicates falling edge on S1_IN_C
S1_IN_A, S1_IN_B, or S1_IN_CIndicates falling edge on S1_IN_A, S1_IN_B, or S1_IN_C
Rising or falling edgeS0_IN_AIndicates assertion/de-assertion of port-side interrupt (Tx_Fault or IntL).
S0_IN_BIndicates that a module has been inserted/removed.
S0_IN_CIndicates presence/absence of optical signal (Rx_LOS) for SFP applications.
S0_IN_A, S0_IN_B, or S0_IN_CIndicates assertion/de-assertion of port-side interrupt, insertion/removal of module, or presence/absence of optical signal (Rx_LOS).
S1_IN_AIndicates rising/falling edge on S1_IN_A
S1_IN_BIndicates rising/falling edge on S1_IN_B
S1_IN_CIndicates rising/falling edge on S1_IN_C
S1_IN_A, S1_IN_B, or S1_IN_CIndicates rising/falling edge on S1_IN_A, S1_IN_B, or S1_IN_C
(1) Example applications assume that S0_IN_A, S0_IN_B, and S0_IN_C are connected to the downstream ports as per the example connection table, Table 7-2.

The FPC202 is also able to generate an interrupt based on pre-fetched data. This is known as a data-driven interrupt. The FPC202 monitors up to four bytes within the pre-fetched range for each port. For each of the bytes, the register offset address is programmed to a local FPC202 register as well as the enable bit fields which will trigger the interrupt. When one of the enabled bits of the four monitored bytes changes state from a '0' to a '1' and stays a '1' for two consecutive periodic pre-fetch cycles (0→1→1), the interrupt is generated and the periodic pre-fetch operation is halted. The FPC202 has four registers per port, which contain the sampled data from the bytes being monitored after the interrupt is triggered. To clear the interrupt, the trigger source byte's sampled data register is read. The periodic pre-fetch must be restarted after the interrupt is cleared with an I2C command. Because it takes two periodic pre-fetch cycles to trigger this interrupt, it may take up to 10 ms for the host to see the trigger after the downstream module's monitored bit field changes for the fastest periodic pre-fetch setting.

The FPC202 also has the ability to generate an interrupt if there is a mishap in the downstream I2C bus. The SDA bus and the SCL bus each have timers that will trigger an interrupt if they are held in a low state too long due to excessive clock stretching or a port error. Once the interrupt is triggered, it is cleared by issuing a port reset on the relevant port. These interrupts are known as SCL Stuck and SDA Stuck interrupts and can be configured individually for each port. By default, the SCL Stuck interrupt will trigger after the SCL bus is held low for 35 ms (typical). This value is configurable individually by port. The SDA Stuck interrupt will trigger after the SDA is held low for 1 s (typical). The user may issue a port reset sequence (9 consecutive SCL clock cycles with the last being an I2C stop condition) or module reset to restore the module to a known state.

When a host-side interrupt is triggered, the host must determine the source and cause of the interrupt. The recommended procedure for identifying the source and cause of an interrupt is as follows:

  1. Read the FPC202 aggregated port interrupt flags of the first FPC202 instance to see which, if any, downstream port triggered the interrupt.
  2. If this instance of the FPC202 has any aggregated port interrupts flagged, read all of the status registers to determine the source of the interrupt and clear it. If an SCL Stuck or SDA Stuck interrupt is triggered, a port reset must be issued and the periodic pre-fetch must be restarted. The host may also perform other housekeeping activities based on the interrupt, such as change the state of the LEDs after a module is no longer present.
  3. Repeat steps 1 and 2 for the next FPC202 instance, until the HOST_INT_N bus is cleared.

This procedure applies to every FPC202 device which is wire-or’ed to the host-side interrupt signal. The total time required for the host to identify the source and cause of the interrupt for an implementation consisting of N total FPC202’s, where all N HOST_INT_N outputs are wire-or’ed together, is as follows:

Tinterrupt = Delay between the IN_* pin changing state and the corresponding FPC202 device triggering an interrupt (50 µs max).

Tread = Time required to read a single register from N FPC202 devices.

For I2C mode, Tread = (9*4*N)/FI2C, where FI2C is the SCL clock frequency.

For SPI mode, Tread = (29*2*N)/FSPI + TOFF-SSN, where FSPI is the SCK clock frequency, and TOFF-SSN is the SS_N off time.

Ttotal = Tinterrupt + 4*Tread

Table 7-4 gives some examples of Ttotal for different I2C/SPI frequencies and different values of N.

Table 7-4 Example Calculations for Determining the Source and Cause of a Host-Side Interrupt
MODEFI2CFSPINTread (ms)Ttotal (ms)
I2C100 kHz–10.361.5
I2C100 kHz–41.445.8
I2C100 kHz–82.8811.6
I2C100 kHz–124.3217.3
I2C400 kHz–10.090.4
I2C400 kHz–40.361.5
I2C400 kHz–80.722.9
I2C400 kHz–121.084.4
I2C1000 kHz–10.00360.1
I2C1000 kHz–40.1440.6
I2C1000 kHz–80.2881.2
I2C1000 kHz–120.4321.8
SPI–1 MHz10.060.3
SPI–1 MHz40.231.0
SPI–1 MHz80.471.9
SPI–1 MHz120.702.8
SPI–10 MHz10.010.1
SPI–10 MHz40.020.1
SPI–10 MHz80.050.2
SPI–10 MHz120.070.3

Request access to the FPC202 Programmer's Guide (SNLU229) here for more details on how to configure the interrupts.