ZHCSVT2A April   2022  – April 2024 BQ76922

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76922
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 Voltage References
    14. 6.14 Coulomb Counter
    15. 6.15 Coulomb Counter Digital Filter (CC1)
    16. 6.16 Current Measurement Digital Filter (CC2)
    17. 6.17 Current Wake Detector
    18. 6.18 Analog-to-Digital Converter
    19. 6.19 Cell Balancing
    20. 6.20 Cell Open Wire Detector
    21. 6.21 Internal Temperature Sensor
    22. 6.22 Thermistor Measurement
    23. 6.23 Internal Oscillators
    24. 6.24 High-side NFET Drivers
    25. 6.25 Comparator-Based Protection Subsystem
    26. 6.26 Timing Requirements – I2C Interface, 100kHz Mode
    27. 6.27 Timing Requirements – I2C Interface, 400kHz Mode
    28. 6.28 Timing Requirements – HDQ Interface
    29. 6.29 Interface Timing Diagrams
    30. 6.30 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Using VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Voltage Calibration (ADC Measurements)
      9. 7.5.9  Voltage Calibration (COV and CUV Protections)
      10. 7.5.10 Current Calibration
      11. 7.5.11 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 LDO Control
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  Fuse Drive
      10. 7.7.10 Cell Open Wire
      11. 7.7.11 Low Frequency Oscillator
      12. 7.7.12 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
  10. 9 Power Supply Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Documentation Support
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, Orderable Information

封装选项

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机械数据 (封装 | 引脚)
  • RSN|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.3 Recommended Operating Conditions

Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBAT Supply voltage Voltage on BAT pin (normal operation) 4.7 27.5 V
VBAT Supply voltage(3) Voltage on BAT pin (OTP programming) 10 12 V
TOTP OTP programming temperature(3) –40 45 °C
VPORA Power-on reset Rising threshold on BAT 3 4 V
VPORA_HYS Power-on reset hysteresis Device shuts down when BAT < VPORA - VPORA_HYS 225 mV
VWAKEONLD Wake on LD voltage Rising edge on LD, with BAT already in valid range 0.8 1.45 2.25 V
VWAKEONTS2 Wake on TS2 voltage Falling edge on TS2, with BAT already in valid range. TS2 will be weakly driven with a 5 V level during shutdown. 0.7 1.1 V
VIN Input voltage range(3) PACK, LD 0 27.5 V
VIN Input voltage range(3) PCHG, PDSG the maximum of VBAT–9 or VLD–9  27.5 V
VIN Input voltage range(3) REG1, RST_SHUT, ALERT, SCL, SDA, CFETOFF, DFETOFF, except when the pin is being used for general purpose ADC input or thermistor measurement. 0 5.5 V
VIN Input voltage range(3) TS1, TS2, CFETOFF, DFETOFF, ALERT, when the pin is configured for general purpose ADC input or thermistor measurement. 0 VREG18 V
VIN Input voltage range(5) SRP, SRN, SRP-SRN (while measuring current) –0.2 0.2 V
VIN Input voltage range(3) SRP, SRN (without measuring current) –0.2 0.75 V
VIN Input voltage range(3)(4) VVC(0) –0.2 0.5 V
VIN Input voltage range(5) VVC(x), 1 ≤ x ≤ 3 maximum of VVC(x–1) – 0.2 or VSS–0.2 minimum of VVC(x–1)+5.5 or VSS+27.5 V
VIN Input voltage range VVC(x), x ≥ 4 maximum of VVC(x–1) – 0.2 or VSS + 2.0 minimum of VVC(x–1) + 5.5 or VSS + 27.5 V
RC External cell input resistance(3) (6) 20 100 Ω
RC External cell input capacitance(3) (6) 0.1 0.22 1 µF
VO Output voltage range LD 27.5 V
VO Output voltage range(5) CHG, DSG, CP1 40 V
TOPR Operating temperature(5) –40 85 °C
VCELL(ACC) Cell voltage measurement accuracy 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 25°C, 1 ≤ x ≤ 5(1)(2) –5 5 mV
VCELL(ACC) Cell voltage measurement accuracy(5) 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 0°C to 60°C, 1 ≤ x ≤ 5(1)(2) –10 10 mV
VCELL(ACC) Cell voltage measurement accuracy(5) –0.2 V < VVC(x) - VVC(x-1) < 5.5 V, TA = -40°C to 85°C, 1 ≤ x ≤ 5(1)(2) –15 15 mV
VSTACK(ACC) Stack voltage (VC5 - VSS) measurement accuracy(5) 0 V < VVC5 - VVSS ≤ 27.5 V, TA = -40°C to 85°C(1) –0.5 0.5 V
VPACK(ACC) PACK pin voltage measurement accuracy(5) 0 V < VPACK - VVSS ≤ 27.5 V, TA = -40°C to 85°C(1) –0.5 0.5 V
VLD(ACC) LD pin voltage measurement accuracy(5) 0 V < VLD - VVSS ≤ 27.5 V, TA = -40°C to 85°C(1) –0.5 0.5 V
(2) While in SLEEP mode, it is important that the cell 1 voltage measurement be validated before being considered valid.  For further information and details, see Cell 1 Voltage Validation during SLEEP Mode.
(3) Specified by design
(4) Voltage on VC0 can extend higher (limited by absolute maximum specification) during cell balancing.
(5) Specified by characterization
(6) Values may need to be optimized during system design and evaluation for best performance