ZHCSVT2A April   2022  – April 2024 BQ76922

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76922
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 Voltage References
    14. 6.14 Coulomb Counter
    15. 6.15 Coulomb Counter Digital Filter (CC1)
    16. 6.16 Current Measurement Digital Filter (CC2)
    17. 6.17 Current Wake Detector
    18. 6.18 Analog-to-Digital Converter
    19. 6.19 Cell Balancing
    20. 6.20 Cell Open Wire Detector
    21. 6.21 Internal Temperature Sensor
    22. 6.22 Thermistor Measurement
    23. 6.23 Internal Oscillators
    24. 6.24 High-side NFET Drivers
    25. 6.25 Comparator-Based Protection Subsystem
    26. 6.26 Timing Requirements – I2C Interface, 100kHz Mode
    27. 6.27 Timing Requirements – I2C Interface, 400kHz Mode
    28. 6.28 Timing Requirements – HDQ Interface
    29. 6.29 Interface Timing Diagrams
    30. 6.30 Typical Characteristics
  8. Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Using VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Voltage Calibration (ADC Measurements)
      9. 7.5.9  Voltage Calibration (COV and CUV Protections)
      10. 7.5.10 Current Calibration
      11. 7.5.11 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 LDO Control
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  Fuse Drive
      10. 7.7.10 Cell Open Wire
      11. 7.7.11 Low Frequency Oscillator
      12. 7.7.12 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
  10. Power Supply Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Documentation Support
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, Orderable Information

封装选项

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订购信息

I2C Communications

The I2C serial communications interface in the BQ76922 device acts as a responder device and supports rates up to 400kHz with an optional CRC check. If the OTP has not been programmed, the BQ76922 device will initially power up by default in 400kHz I2C mode. The OTP setting can be programmed on the manufacturing line, then when the device powers up, it will automatically enter the selected mode per OTP setting. The host can also change the I2C speed setting while in CONFIG_UPDATE mode, then the new speed setting will take effect upon exit of CONFIG_UPDATE mode. Alternatively, the host can use the SWAP_TO_I2C() subcommand to change the communications interface to I2C immediately.

The I2C device address (as an 8bit value including responder address and R/W bit) is set by default as 0x10 (write), 0x11 (read), which can be changed by configuration setting.

The communications interface includes programmable timeout capability, this should only be used if the bus will be operating at 100kHz or 400kHz. If this is enabled with the device set to 100kHz mode, then the device will reset the communications interface logic if a clock is detected low longer than a tTIMEOUT of 25ms to 35ms, or if the cumulative clock low responder extend time exceeds approximately 25ms, or if the cumulative clock low controller extend time exceeds 10ms. If the timeouts are enabled with the device set to 400kHz mode, then the device will reset the communications interface logic if a clock is detected low longer than tTIMEOUT of 5ms to 20ms. The bus also includes a long-term timeout if the SCL pin is detected low for more than 2 seconds, which applies whether or not the timeouts above are enabled.

An I2C write transaction is shown in I2C Write. Block writes are allowed by sending additional data bytes before the Stop. The I2C logic will auto-increment the register address after each data byte.

When enabled, the CRC is calculated as follows:

  • Note that the CRC is reset after each data byte and after each stop.
  • In a single-byte write transaction, the CRC is calculated over the responder address, register address, and data.
  • In a block write transaction, the CRC for the first data byte is calculated over the responder address, register address, and data. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.

When the responder detects an invalid CRC, the I2C responder will NACK the CRC, which causes the I2C responder to go to an idle state.


GUID-7A390402-C61F-46E8-8342-20B9CC47BC66-low.gif

Figure 7-6 I2C Write

I2C Read with Repeated Start shows a read transaction using a Repeated Start.


GUID-2D99981C-EB89-4703-92BA-4C62900F978F-low.gif

Figure 7-7 I2C Read with Repeated Start

I2C Read without Repeated Start shows a read transaction where a Repeated Start is not used, for example if not available in hardware. For a block read, the controller ACK’s each data byte except the last and continues to clock the interface. The I2C block will auto-increment the register address after each data byte.

When enabled, the CRC for a read transaction is calculated as follows:

  • Note that the CRC is reset after each data byte and after each stop.
  • In a single-byte read transaction using a repeated start, the CRC is calculated beginning at the first start, so will include the responder address, the register address, then the responder address with read bit set, then the data byte.
  • In a single-byte read transaction using a stop after the initial register address, the CRC is reset after the stop, so will only include the responder address with read bit set and the data byte.
  • In a block read transaction using repeated starts, the CRC for the first data byte is calculated beginning at the first start and will include the responder address, the register address, then the responder address with read bit set, then the data byte. The CRC for subsequent data bytes is calculated over the data byte only.
  • In a block read transaction using a stop after the initial register address, the CRC is reset after the stop, so will only include the responder address with read bit set and the first data byte. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.

When the controller detects an invalid CRC, the I2C controller will NACK the CRC, which causes the I2C responder to go to an idle state.


GUID-E15DDBA3-EFFA-4B6E-A58A-C61E511B2826-low.gif

Figure 7-8 I2C Read Without Repeated Start