ZHCSVT2A April 2022 – April 2024 BQ76922
PRODUCTION DATA
The I2C serial communications interface in the BQ76922 device acts as a responder device and supports rates up to 400kHz with an optional CRC check. If the OTP has not been programmed, the BQ76922 device will initially power up by default in 400kHz I2C mode. The OTP setting can be programmed on the manufacturing line, then when the device powers up, it will automatically enter the selected mode per OTP setting. The host can also change the I2C speed setting while in CONFIG_UPDATE mode, then the new speed setting will take effect upon exit of CONFIG_UPDATE mode. Alternatively, the host can use the SWAP_TO_I2C() subcommand to change the communications interface to I2C immediately.
The I2C device address (as an 8bit value including responder address and R/W bit) is set by default as 0x10 (write), 0x11 (read), which can be changed by configuration setting.
The communications interface includes programmable timeout capability, this should only be used if the bus will be operating at 100kHz or 400kHz. If this is enabled with the device set to 100kHz mode, then the device will reset the communications interface logic if a clock is detected low longer than a tTIMEOUT of 25ms to 35ms, or if the cumulative clock low responder extend time exceeds approximately 25ms, or if the cumulative clock low controller extend time exceeds 10ms. If the timeouts are enabled with the device set to 400kHz mode, then the device will reset the communications interface logic if a clock is detected low longer than tTIMEOUT of 5ms to 20ms. The bus also includes a long-term timeout if the SCL pin is detected low for more than 2 seconds, which applies whether or not the timeouts above are enabled.
An I2C write transaction is shown in I2C Write. Block writes are allowed by sending additional data bytes before the Stop. The I2C logic will auto-increment the register address after each data byte.
When enabled, the CRC is calculated as follows:
The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.
When the responder detects an invalid CRC, the I2C responder will NACK the CRC, which causes the I2C responder to go to an idle state.
I2C Read with Repeated Start shows a read transaction using a Repeated Start.
I2C Read without Repeated Start shows a read transaction where a Repeated Start is not used, for example if not available in hardware. For a block read, the controller ACK’s each data byte except the last and continues to clock the interface. The I2C block will auto-increment the register address after each data byte.
When enabled, the CRC for a read transaction is calculated as follows:
The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.
When the controller detects an invalid CRC, the I2C controller will NACK the CRC, which causes the I2C responder to go to an idle state.