A simplified application schematic for a
5-series battery pack is shown in Figure 8-1, using the BQ76922 together with an external secondary protector and a host
microcontroller. This configuration uses CHG and DSG FETs in series, together with high-side
PFET devices used to implement precharge and predischarge functionality. Several points to
consider in an implementation are included below:
- The external NPN BJT used for the REGIN
preregulator can be configured with its collector routed either to the cell battery stack
or the middle of the protection FETs.
- A diode is recommended in the drain
circuit of the external NPN BJT, which avoids reverse current flow from the BREG pin
through the BJT base to collector in the event of a pack short circuit. This diode can be
a Schottky diode if low voltage pack operation is needed, or a conventional diode can be
used otherwise.
- A series diode is recommended at the BAT
pin, together with a capacitor from the pin to VSS. These components allow the device to
continue operating for a short time when a pack short circuit occurs, which may cause the
PACK+ and top-of-stack voltages to drop to approximately 0V. In this case, the diode
prevents the BAT pin from being pulled low with the stack, and the device will continue to
operate, drawing current from the capacitor. Generally operation is only required for a
short time, until the device detects the short circuit event and disables the DSG FET. A
Schottky diode can be used if low voltage pack operation is needed, or a conventional
diode can be used otherwise.
- The diode in the BAT connection and the
diode in the BJT collector should not be shared, since then the REG0 circuit might
discharge the capacitor on BAT too quickly during a short circuit event.
- The recommended voltage range on the VC0
to VC3A pins extends to –0.2V. This can be used, for example, to measure a differential
voltage that extends slightly below ground, such as the voltage across a second sense
resistor in parallel with that connected to the SRP and SRN pins.
- If a system does not use high-side
protection FETs, then the PACK pin can be connected through a series 10kΩ resistor to the
top of stack. The LD pin can be connected to VSS. In this case, the LD pin can also be
controlled separately, in order to wake the device from SHUTDOWN mode, such as through
external circuitry which holds the LD pin at the voltage of VSS while the device stays in
SHUTDOWN, and to be driven above a voltage of VWAKEONLD in order to wake from
SHUTDOWN.
- TI recommends using 100Ω resistors in
series with the SRP and SRN pins, and a 100nF with optional 100pF differential filter
capacitance between the pins for filtering. The routing of these components, together with
the sense resistor, to the pins should be minimized and fully symmetric, with all
components recommended to stay on the same side of the PCB with the device. Capacitors
should not be connected from the pins to VSS.
- Due to thermistors often being attached
to cells and possibly needing long wires to connect back to the device, it may be helpful
to add a capacitor from the thermistor pin to the device VSS. However, it is important to
not use too large of a value of capacitor, since this will affect the settling time when
the thermistor is biased and measured periodically. A rule of thumb is to keep the time
constant of the circuit < 5% of the measurement time. When
Settings:Configuration:Power Config[FASTADC] = 0, the measurement time
is approximately 3 ms, and with [FASTADC] = 1 the measurement time is halved
to approximately 1.5ms. When using the 18kΩ pullup resistor with the thermistor, the time
constant will generally be less than (18kΩ) × C, so a capacitor less than 4nF is
recommended. When using the 180kΩ pullup resistor, the capacitor should be less than
400pF.
- The integrated charge pump generates a
voltage on the CP1 capacitor, requiring approximately 60ms to charge up to approximately
11V when first enabled, when using the recommended 470nF capacitor value. When the CHG or
DSG drivers are enabled, charge redistribution occurs from the CP1 capacitor to the CHG
and DSG capacitive FET loads. This will generally result in a brief drop in the voltage on
CP1, which is then replenished by the charge pump. If the FET capacitive loading is large,
such that at FET turn-on the voltage on CP1 drops below an acceptable level for the
application, then the value of the CP1 capacitor can be increased. This has the drawback
of requiring a longer startup time for the voltage on CP1 when the charge pump is first
powered on, and so should be evaluated to ensure it is acceptable in the system. For
example, if the CHG and DSG FETs are enabled simultaneously and their combined gate
capacitance is approximately 400nF, then changing CP1 to a value of 2200nF will result in
the 11V charge pump level dropping to approximately 9V, before being restored to the 11V
level by the charge pump.
A full schematic of a basic monitor circuit
based on the BQ76922 for a 5-series battery pack is shown below. The board layout for this
design is shown in Section 10.2.