ZHCSVT2A April   2022  – April 2024 BQ76922

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76922
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 Voltage References
    14. 6.14 Coulomb Counter
    15. 6.15 Coulomb Counter Digital Filter (CC1)
    16. 6.16 Current Measurement Digital Filter (CC2)
    17. 6.17 Current Wake Detector
    18. 6.18 Analog-to-Digital Converter
    19. 6.19 Cell Balancing
    20. 6.20 Cell Open Wire Detector
    21. 6.21 Internal Temperature Sensor
    22. 6.22 Thermistor Measurement
    23. 6.23 Internal Oscillators
    24. 6.24 High-side NFET Drivers
    25. 6.25 Comparator-Based Protection Subsystem
    26. 6.26 Timing Requirements – I2C Interface, 100kHz Mode
    27. 6.27 Timing Requirements – I2C Interface, 400kHz Mode
    28. 6.28 Timing Requirements – HDQ Interface
    29. 6.29 Interface Timing Diagrams
    30. 6.30 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Using VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Voltage Calibration (ADC Measurements)
      9. 7.5.9  Voltage Calibration (COV and CUV Protections)
      10. 7.5.10 Current Calibration
      11. 7.5.11 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 LDO Control
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  Fuse Drive
      10. 7.7.10 Cell Open Wire
      11. 7.7.11 Low Frequency Oscillator
      12. 7.7.12 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
  10. 9 Power Supply Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Documentation Support
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RSN|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.2.1 Design Requirements (Example)

Table 8-1 BQ76922 Design Requirements
DESIGN PARAMETEREXAMPLE VALUE
Minimum system operating voltage12.5V
Cell minimum operating voltage2.5V
Series cell count5
Sense resistor1mΩ
Number of thermistors2 (using TS1 and TS2 pins, both for cells)
Charge voltage22V
Maximum charge current3.0A
Peak discharge current20.0A
Configuration settingsprogrammed in OTP during customer production
Protection subsystem configurationSeries FET configuration, device monitors, disables FETs upon fault, recovers autonomously
OV protection threshold4.30V
OV protection delay500ms
OV protection recovery hysteresis100mV
UV protection threshold2.5V
UV protection delay20ms
UV protection recovery hysteresis100mV
SCD protection threshold80mV (corresponding to a nominal 80A, based on a 1mΩ sense resistor)
SCD protection delay50µs
OCD1 protection threshold68mV (corresponding to a nominal 68A, based on a 1mΩ sense resistor)
OCD1 protection delay10 ms
OCD2 protection threshold56mV (corresponding to a nominal 56A, based on a 1mΩ sense resistor)
OCD2 protection delay80ms
OCD3 protection threshold28mV (corresponding to a nominal 28A, based on a 1mΩ sense resistor)
OCD3 protection delay160ms
OCC protection threshold8mV (corresponding to a nominal 8A, based on a 1mΩ sense resistor)
OCC protection delay160ms
OTD protection threshold60°C
OTD protection delay2s
OTC protection threshold45°C
OTC protection delay2s
UTD protection threshold–20°C
UTD protection delay10s
UTC protection threshold0°C
UTC protection delay5s
Host watchdog timeout protection delay5s
CFETOFF pin functionalityUse as CFETOFF, polarity = normally high, driven low to disable FET
DFETOFF pin functionalityUse as DFETOFF, polarity = normally high, driven low to disable FET
ALERT pin functionalityUse as ALERT interrupt pin, polarity = driven low when active, hi-Z otherwise
REG1 LDO UsageUse for 3.3V output
Cell balancingEnabled when imbalance exceeds 100mV