ZHCSCL7C May   2014  – April 2021 AFE4403

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Device Family Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Third LED Support
        2. 8.3.5.2 Transmitter Power Path
        3. 8.3.5.3 LED Power Reduction During Periods of Inactivity
        4. 8.3.5.4 LED Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
        3. 8.4.1.3 Dynamic Power-Down Mode
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Consumption Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Typical Characteristics

At PRF = 100 Hz, 25% duty cycle, RF = 500 kΩ, CF is adjusted to keep TIA time constant at 1/10th of sampling duration, All supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector CIN = 50 pF, TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless otherwise noted.

GUID-D847C72C-9991-4091-8B66-F685C3BD7CAC-low.pngFigure 7-5 Receiver Currents vs Receiver Supply Voltage
GUID-16BBE017-B39E-40B7-9C9C-A44CACED14C6-low.png
PRF = 150 Hz
Figure 7-7 Receiver Currents (Analog and Digital) vs Clock Divider Ratio
GUID-78D05643-FF6F-4373-B800-EA01553F522A-low.png
PRF = 100 Hz LED pulse = 100 µs
All four DYNAMIC bits set to 1
Figure 7-9 Receiver Current (Analog and Digital) vs Dynamic Power-Down Duty Cycle
GUID-1633395F-FE52-4F02-B453-CEA4E84C9EB8-low.png
500-Hz PRF
Figure 7-11 SNR over Nyquist Bandwidth vs Duty Cycle (Input Current with Tx-Rx Loopback)
GUID-65ACA1D9-5BF1-4BDC-85C1-6FB6B4F9B9B7-low.pngFigure 7-13 Receiver SNR over Nyquist Bandwidth vs Duty Cycle (Different Gain Settings)
GUID-EC1E784F-27A3-4BB9-96B4-9B09812D6B75-low.pngFigure 7-15 Receiver SNR in 20-Hz BW vs Duty Cycle (Different Gain Settings)
GUID-C221F731-514A-4020-9B37-10E0A9920632-low.pngFigure 7-17 Receiver SNR over Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging)
GUID-4E3E160F-18E3-4E43-A6E6-1685CC75CD4F-low.pngFigure 7-19 Receiver SNR in 20-Hz BW vs Duty Cycle (Different PRFs)
GUID-A3635300-2FA7-4923-B41F-EEEAF794B19C-low.png
Active window = 500 µs LED pulse = 100 µs
All four DYNAMIC bits set to 1
Figure 7-21 Receiver SNR in 20-Hz BW in Dynamic Power-Down Mode vs PRF
GUID-55110915-E705-4A11-92E5-BAAD54F54F4D-low.png
PRF = 100 Hz LED pulse = 100 µs
All four DYNAMIC bits set to 1
Figure 7-23 Receiver SNR over Nyquist Bandwidth vs Dynamic Power-Down Duty Cycle
GUID-0CD53C14-8592-4C20-9C75-C895591BE640-low.png
LED pulse = 100 µs Pleth current = 1 µA
Figure 7-25 SNR in 20-Hz Bandwidth vs Temperature (Tx-Rx Loopback)
GUID-D5117FCB-C4B8-4858-A441-5CBDDEBA09BC-low.png
Stage 2 enabled
Figure 7-27 Receiver SNR over Nyquist Bandwidth vs Duty Cycle (Different Stage 2 Gain Settings)
GUID-9CDDF278-F8D8-4254-B7D5-7B18F91BFEC4-low.png
RF = 250 kΩ PRF = 100 Hz ADC averaging = 1
Figure 7-29 Receiver Input-Referred Noise Current vs Internal Clock Frequency
GUID-96EA57C3-1A95-4A2C-8715-FF25BDC317E3-low.png
PRF = 500 Hz
DAC current is set such that ADC output is 50 %FS
Figure 7-31 SNR in 20-Hz BW vs Duty Cycle (TX_REF Voltage with Tx-Rx Loopback)
GUID-0F13E06F-6413-4019-827A-D46B958E295C-low.png
TX_REF = 0.25 V
Figure 7-33 Transmitter Current linearity
GUID-1C98BB51-3E0B-40FB-BAFC-DE0817E67F87-low.pngFigure 7-35 Transmitter Current vs TX_REF Voltage (Multiple DAC Settings)
GUID-5A689ACF-1C6B-4EC3-A1D7-08CE4ED65D97-low.png
LED current = 0 mA
Figure 7-6 Transmitter Currents vs Transmitter Supply Voltage
GUID-3A145A06-B442-4826-A615-606CF87C0663-low.png
Active window = 500 µs LED pulse = 100 µs
All four DYNAMIC bits set to 1
Figure 7-8 Receiver Current vs PRF in Dynamic Power-Down Mode
GUID-C30A8472-7A9F-42CD-AC68-B2D46ABE60D4-low.png
Figure 7-10 Filter Response vs Duty cycle
GUID-2E5DC8BA-1909-4FFE-AC29-A6F5ABDFF0F9-low.png
500-Hz PRF
Figure 7-12 Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Input Current with Tx-Rx Loopback)
GUID-979A7FDE-4988-460B-BCC1-3DA6398875B1-low.pngFigure 7-14 Receiver Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Different Gain Settings)
GUID-C6C626A7-ADE0-4151-BD8F-E3CD61C1252C-low.pngFigure 7-16 Receiver Input-Referred Noise Current in 20-Hz BW vs Duty Cycle (Different Gain Settings)
GUID-CEF53B82-E9CB-4EE1-BF0E-94CC384FDC7F-low.pngFigure 7-18 Receiver Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging)
GUID-3DD990A8-CCDD-45A0-86CD-3AC8B4495DF9-low.pngFigure 7-20 Receiver Input Referred Noise in 20-Hz BW vs Duty Cycle (Different PRFs)
GUID-2865AB94-60E5-4050-BDC5-8D95A63DBD62-low.png
Active window = 500 µs LED pulse = 100 µs
All four DYNAMIC bits set to 1
Figure 7-22 Receiver Input-Referred Noise in 20-Hz BW in Dynamic Power-Down Mode vs PRF
GUID-93FA4DF2-27D6-4D7E-8D50-3DA572BA9046-low.png
PRF = 100 Hz LED pulse = 100 µs
All four DYNAMIC bits set to 1
Figure 7-24 Receiver Input-Referred Noise over Nyquist Bandwidth vs Dynamic Power-Down Duty Cycle
GUID-5216B7A1-131B-42FC-9D1E-3954C0B0E4AD-low.png
LED pulse = 100 µs Pleth current = 1 µA
Figure 7-26 Input-Referred Noise Current in 20-Hz BW vs Temperature (TX-Rx Loopback)
GUID-F4C444BD-B05D-472A-823D-17534EA60DFB-low.png
Stage 2 enabled
Figure 7-28 Receiver Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Different Stage 2 Gain Settings)
GUID-506F7BDD-7BBB-4EB2-B919-9415F4A1DB86-low.png
TX_REF = 0.25 V
Figure 7-30 Transmitter DAC Current Step Error
GUID-2A9751FE-DFF9-4536-8DDB-245C26C01E02-low.png
PRF = 500 Hz
DAC current is set such that ADC output is 50 %FS
Figure 7-32 Input Referred Noise Current in 20-Hz BW vs Duty Cycle (TX_REF Voltage with Tx-Rx Loopback)
GUID-93CBDCEC-3723-4095-9A4B-4EE041207BE3-low.png
LED current = 48 mA 100 devices on tester
Figure 7-34 Transmitter Current Across Devices