ZHCSCL7C May   2014  – April 2021 AFE4403

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Family Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Third LED Support
        2. 8.3.5.2 Transmitter Power Path
        3. 8.3.5.3 LED Power Reduction During Periods of Inactivity
        4. 8.3.5.4 LED Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
        3. 8.4.1.3 Dynamic Power-Down Mode
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Consumption Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6.1 AFE Register Map

The AFE consists of a set of registers that can be used to configure it, such as receiver timings, I-V amplifier settings, transmit LED currents, and so forth. The registers and their contents are listed in Table 8-8. These registers can be accessed using the AFE SPI interface.

Table 8-8 AFE Register Map
NAME REGISTER CONTROL(1) ADDRESS REGISTER DATA
Hex Dec 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONTROL0 W 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_RST DIAG_EN TIM_COUNT_RST SPI_READ
LED2STC R/W 01 1 0 0 0 0 0 0 0 0 LED2STC[15:0]
LED2ENDC R/W 02 2 0 0 0 0 0 0 0 0 LED2ENDC[15:0]
LED2LEDSTC R/W 03 3 0 0 0 0 0 0 0 0 LED2LEDSTC[15:0]
LED2LEDENDC R/W 04 4 0 0 0 0 0 0 0 0 LED2LEDENDC[15:0]
ALED2STC R/W 05 5 0 0 0 0 0 0 0 0 ALED2STC[15:0]
ALED2ENDC R/W 06 6 0 0 0 0 0 0 0 0 ALED2ENDC[15:0]
LED1STC R/W 07 7 0 0 0 0 0 0 0 0 LED1STC[15:0]
LED1ENDC R/W 08 8 0 0 0 0 0 0 0 0 LED1ENDC[15:0]
LED1LEDSTC R/W 09 9 0 0 0 0 0 0 0 0 LED1LEDSTC[15:0]
LED1LEDENDC R/W 0A 10 0 0 0 0 0 0 0 0 LED1LEDENDC[15:0]
ALED1STC R/W 0B 11 0 0 0 0 0 0 0 0 ALED1STC[15:0]
ALED1ENDC R/W 0C 12 0 0 0 0 0 0 0 0 ALED1ENDC[15:0]
LED2CONVST R/W 0D 13 0 0 0 0 0 0 0 0 LED2CONVST[15:0]
LED2CONVEND R/W 0E 14 0 0 0 0 0 0 0 0 LED2CONVEND[15:0]
ALED2CONVST R/W 0F 15 0 0 0 0 0 0 0 0 ALED2CONVST[15:0]
ALED2CONVEND R/W 10 16 0 0 0 0 0 0 0 0 ALED2CONVEND[15:0]
LED1CONVST R/W 11 17 0 0 0 0 0 0 0 0 LED1CONVST[15:0]
LED1CONVEND R/W 12 18 0 0 0 0 0 0 0 0 LED1CONVEND[15:0]
ALED1CONVST R/W 13 19 0 0 0 0 0 0 0 0 ALED1CONVST[15:0]
ALED1CONVEND R/W 14 20 0 0 0 0 0 0 0 0 ALED1CONVEND[15:0]
ADCRSTSTCT0 R/W 15 21 0 0 0 0 0 0 0 0 ADCRSTCT0[15:0]
ADCRSTENDCT0 R/W 16 22 0 0 0 0 0 0 0 0 ADCRENDCT0[15:0]
ADCRSTSTCT1 R/W 17 23 0 0 0 0 0 0 0 0 ADCRSTCT1[15:0]
ADCRSTENDCT1 R/W 18 24 0 0 0 0 0 0 0 0 ADCRENDCT1[15:0]
ADCRSTSTCT2 R/W 19 25 0 0 0 0 0 0 0 0 ADCRSTCT2[15:0]
ADCRSTENDCT2 R/W 1A 26 0 0 0 0 0 0 0 0 ADCRENDCT2[15:0]
ADCRSTSTCT3 R/W 1B 27 0 0 0 0 0 0 0 0 ADCRSTCT3[15:0]
ADCRSTENDCT3 R/W 1C 28 0 0 0 0 0 0 0 0 ADCRENDCT3[15:0]
PRPCOUNT R/W 1D 29 0 0 0 0 0 0 0 0 PRPCT[15:0]
CONTROL1 R/W 1E 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEREN NUMAV[7:0]
SPARE1 N/A 1F 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TIAGAIN R/W 20 32 0 0 0 0 0 0 0 0 ENSEPGAN STAGE2EN1 0 0 0 STG2GAIN1[2:0] CF_LED1[4:0] RF_LED1[2:0]
TIA_AMB_GAIN R/W 21 33 0 0 0 0 AMBDAC[3:0] FLTRCNRSEL STAGE2EN 0 0 0 STG2GAIN2[2:0] CF_LED[4:0] RF_LED[2:0]
LEDCNTRL R/W 22 34 0 0 0 0 0 0 LED_RANGE[1:0] LED1[7:0] LED2[7:0]
CONTROL2 R/W 23 35 0 0 0 DYNAMIC1 0 TX_REF1 TX_REF0 0 0 DYNAMIC2 0 0 TXBRGMOD DIGOUT_TRISTATE XTALDIS EN_SLOW_DIAG 0 0 0 DYNAMIC3 DYNAMIC4 PDNTX PDNRX PDNAFE
SPARE2 N/A 24 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPARE3 N/A 25 37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPARE4 N/A 26 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED1 N/A 27 39 X X X X X X X X X X X X X X X X X X X X X X X X
RESERVED2 N/A 28 40 X X X X X X X X X X X X X X X X X X X X X X X X
ALARM R/W 29 41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LED2VAL R 2A 42 LED2VAL[23:0]
ALED2VAL R 2B 43 ALED2VAL[23:0]
LED1VAL R 2C 44 LED1VAL[23:0]
ALED1VAL R 2D 45 ALED1VAL[23:0]
LED2-ALED2VAL R 2E 46 LED2-ALED2VAL[23:0]
LED1-ALED1VAL R 2F 47 LED1-ALED1VAL[23:0]
DIAG R 30 48 0 0 0 0 0 0 0 0 0 0 0 PD_ALM LED_ALM LED2OPEN LED1OPEN LEDSC OUTNSHGND OUTPSHGND PDOC PDSC INNSCGND INPSCGND INNSCLED INPSCLED
CONTROL3 R/W 31 49 0 0 0 0 0 0 0 0 TX3_MODE 0 0 0 0 0 0 0 0 0 0 SOMI_TRI CLKOUT_TRI CLKDIV[2:0]
PDNCYCLESTC R/W 32 50 0 0 0 0 0 0 0 0 PDNCYCLESTC[15:0]
PDNCYCLEENDC R/W 33 51 0 0 0 0 0 0 0 0 PDNCYCLEENDC[15:0]
(1) R = read only, R/W = read or write, N/A = not available, and W = write only.