ZHCSD79A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
The ADS54J54 requires a fully differential analog input with a full-scale range not to exceed 1.25 V peak to peak, biased to a common mode voltage of 2.0 V. In addition the input circuit must provide proper transmission line termination (or proper load resistors in an amplifier-based solution) so the input of the impedance of the ADC analog inputs should be considered as well.
The clocking solution will have a direct impact on performance in terms of SNR, as shown in Figure 103. The ADS54J54 is capable of a typical SNR of 66 dBFS for input frequencies of about 100 MHz (in 14-bit bypass digital mode), so we will want to have a clocking solution that can preserve this level of performance.