ZHCSD79A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
DIGITAL INPUTS: SRESETb, SCLK, SDENb, SDATA, ENABLE, OVRA, OVRC, SYSREFCDP, SYSREFCDM | |||||
High-level input voltage | All digital inputs support 1.8-V and 3.3-V logic levels | 1.2 | V | ||
Low-level input voltage | 0.4 | V | |||
High-level input current | 50 | µA | |||
Low-level input current | –50 | µA | |||
Input capacitance | 4 | pF | |||
DIGITAL OUTPUTS: SDOUT, OVRA, OVRB, OVRC, OVRD | |||||
High-level output voltage | ILoad = –100 µA | DVDD – 0.2 | DVDD | V | |
Low-level output voltage | 0.2 | V | |||
DIGITAL INPUTS:
SYNCbABP/M, SYNCbCDP/M, SYSREFABP/M, SYSREFCDP/M |
|||||
Input voltage VID | 250 | 350 | 450 | mV | |
Input common mode voltage VCM | 0.4 | 0.9 | 1.4 | V | |
tS_SYSREFxx | Referenced to rising edge of input clock | 100 | ps | ||
tH_SYSREFxx | Referenced to rising edge of input clock | 100 | ps |