ZHCSD79A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 1 | 1 | 1 | 1 | 1 | JESD SLEEP MODES – SPI |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D15:D0 | JESD SLEEP MODES – SPI | R/W | 11
1111 1111 |
Power-down function controlled via SPI. When a bit is set to 0, the function is powered down when ENABLE pin is high. However register 0x1E has higher priority. For example, if D9 (JESD PLL channel CD) in 0x1E is enabled, it cannot be powered down with the ENABLE pin.
D9 = JESD PLL channel CD D8 = JESD PLL channel AB D7 = Lane DD1 D6 = Lane DD0 D5 = Lane DC1 D4 = Lane DC0 D3 = Lane DB1 D2 = Lane DB0 D1 = Lane DA1 D0 = Lane DA0 |
SPACE
Description | |
---|---|
00 0000 0000 | Global power down |
00 0000 0000 | Standby |
11 0000 0000 | Deep sleep |
11 0000 0000 | Light sleep |
11 1111 1111 | Normal operation (default) |
Control power down function through ENABLE pin:
Control power down function through SPI (ENABLE pin always high):