ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
To include more or fewer secondary TAPS in the scan chain, the debugger must use the ICEPick TAP router to program the TAPs. At its root, ICEPick is a scan-path linker that lets the debugger selectively choose which subsystem TAPs are accessible through the device-level debug interface. Each secondary TAP can be dynamically included in or excluded from the scan path. From external JTAG interface point of view, secondary TAPS that are not selected appear not to exist.
There are two types of components connected through ICEPick to the external debug interface:
Table 11-57 shows the ICEPick secondary taps in the system. For more details on the test related P1500 TAPs, see the DFTSS specification.
TAP # | TYPE | NAME | IR SCAN LENGTH | ACCESS IN SECURE DEVICE | DESCRIPTION |
---|---|---|---|---|---|
0 | n/a | n/a | n/a | No | Reserved (This is an internal TAP and not exposed at the DEBUGSS boundary) |
1 | JTAG | C66x CorePac0 | 38 | No | C66x CorePac0 |
2 | JTAG | C66x CorePac1 | 38 | No | C66x CorePac1 |
3 | JTAG | C66x CorePac2 | 38 | No | C66x CorePac2 |
4 | JTAG | C66x CorePac3 | 38 | No | C66x CorePac3 |
5 | JTAG | C66x CorePac4 | 38 | No | C66x CorePac4 (66AK2H12/14 only) |
6 | JTAG | C66x CorePac5 | 38 | No | C66x CorePac5 (66AK2H12/14 only) |
7 | JTAG | C66x CorePac6 | 38 | No | C66x CorePac6 (66AK2H12/14 only) |
8 | JTAG | C66x CorePac7 | 38 | No | C66x CorePac7 (66AK2H12/14 only) |
9..13 | JTAG | Reserved | NA | No | Spare ports for future expansion |
14 | CS | CS_DAP (APB-AP) | 4 | No | ARM A15 Cores (This is an internal TAP and not exposed at the DEBUGSS boundary) |
CS_DAP (AHB-AP) | PDSP Cores (This is an internal TAP and not exposed at the DEBUGSS boundary) |
For more information on ICEPick, see the KeyStone II Architecture Debug and Trace User’s Guide.