ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
This register is used to select the module clocks that must maintain their clocking without pausing through nonpower-on reset. Setting any of these bits effectively blocks reset to all Main PLL control registers in order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting the module-specific bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in the PSC to reset-isolate a particular module. For more information on the MDCTLx register, see the KeyStone Architecture Power Sleep Controller (PSC) User's Guide. The RSISO is shown in Figure 11-16 and described in Table 11-24.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Reserved | SRIOISO | SRISO | Reserved | Rsvd | Reserved | |||||||||||||||||||||||||
R-0x0000 | R-0x00 | R/W-0 | R/W-0 | R-0x0 | R/W-0 | R-000 |
Legend: R = Read only; R/W = Read/Write; – n = value after reset |
Bit | Field | Description |
---|---|---|
31-10 | Reserved | Reserved. |
9 | SRIOISO | Isolate SRIO module control
|
8 | SRISO | Isolate SmartReflex control
|
7-4 | Reserved | Reserved |
3 | Reserved | Reserved |
2-0 | Reserved | Reserved |