ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
The PLL controller clock align control register (ALNCTL) is shown in Figure 11-10 and described in Table 11-18.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | ALN4 | ALN3 | Reserved | ||||||||||||||||||||||||||||
R-0 | R/W-1 | R/W-1 | R-0 |
Legend: R/W = Read/Write; R = Read only; – n = value after reset, for reset value |
Bit | Field | Description |
---|---|---|
31-5 | Reserved | Reserved. This location is always read as 0. A value written to this field has no effect. |
4-3 | ALN[4:3] | SYSCLKn alignment. Do not change the default values of these fields.
|
2-0 | Reserved | Reserved. This location is always read as 0. A value written to this field has no effect. |