ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
Whenever a different ratio is written to the PLLDIVn registers, the PLL CTL flags the change in the DCHANGE status register. During the GO operation, the PLL controller changes only the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other clocks. The PLLDIV divider ratio change status register is shown in Figure 11-11 and described in Table 11-19.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SYS4 | SYS3 | Reserved | ||||||||||||||||||||||||||||
R-0 | R/W-1 | R/W-1 | R-0 |
Legend: R/W = Read/Write; R = Read only; – n = value after reset, for reset value |
Bit | Field | Description |
---|---|---|
31-5 | Reserved | Reserved. This bit location is always read as 0. A value written to this field has no effect. |
4-3 | SYS[4:3] | Identifies when the SYSCLKn divide ratio has been modified.
|
2-0 | Reserved | Reserved. This bit location is always read as 0. A value written to this field has no effect. |