ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the Main PLL controller for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through an unlocking sequence using the KICK0 and KICK1 registers. These registers reset only on a POR reset.
For valid configurable values of the MAINPLLCTL registers, see Section 10.1.4. See Section 10.2.3.4 for the address location of the KICK registers and their locking and unlocking sequences.
See Figure 11-17 and Table 11-25 for MAINPLLCTL0 details and Figure 11-18 and Table 11-26 for MAINPLLCTL1 details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BWADJ[7:0] | Reserved | PLLM[12:6] | Reserved | PLLD | |||||||||||||||||||||||||||
RW-0000 0101 | RW – 0000 0 | RW-0000000 | RW-000000 | RW-000000 |
Legend: RW = Read/Write; – n = value after reset |
Bit | Field | Description |
---|---|---|
31-24 | BWADJ[7:0] | BWADJ[11:8] and BWADJ[7:0] are in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1. |
23-19 | Reserved | Reserved |
18-12 | PLLM[12:6] | 7-bits of a 13-bit field PLLM that selects the values for the multiplication factor. PLLM field is loaded with the multiply factor minus 1.
The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL Controller and the PLLM[12:6] bits are controlled by the above chip-level register. MAINPLLCTL0 register PLLM[12:6] bits should be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the Main PLL is also controlled by the SECCTL register in the PLL Controller. See the Section 11.5.2.1 for more details. |
11-6 | Reserved | Reserved |
5-0 | PLLD | A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value minus 1. |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | ENSAT | Reserved | BWADJ[11:8] | ||||||||||||||||||||||||||||
RW-0000000000000000000000000 | RW-0 | R-00 | RW- 0000 |
Legend: RW = Read/Write; – n = value after reset |
Bit | Field | Description |
---|---|---|
31-7 | Reserved | Reserved |
6 | ENSAT | Needs to be set to 1 for proper PLL operation |
5-4 | Reserved | Reserved |
3-0 | BWADJ[11:8] | BWADJ[11:8] and BWADJ[7:0] are in MAINPLLCTL0 and MAINPLLCTL1 registers. BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) – 1. |