ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
The RBL also provides an option to configure the DDR table before loading the image into the external memory. More information on how to configure the DDR3, see the KeyStone Architecture DSP Bootloader User's Guide. The configuration table for DDR3 is shown in Table 10-26
BYTE OFFSET | NAME | DESCRIPTION |
---|---|---|
0 | Enable bitmap MSW | Bits 31:0 of the PLL/EMIF enable bitmap. Bit 0 corresponds to the PLL config, Bit 1 to the SDRAM configuration register. There are 24 valid bits in this field (with the MSB corresponding to Rw/exc thresh). |
4 | Enable bitmap SLSW | Bits 31:0 of the chip level register enable bit map. Bit 0 corresponds to chip level configuration register 0. |
8 | Enable bitmap LSW | Bits 60:32 of the chip level register enable bit map. Bit 0 corresponds to chip level configuration register 32. |
12 | PLL Predivier | PLL Predivision (1 = divide by 1, 2 = divide by 2, and so on) |
16 | PLL Multiplier | PLL Multiplication |
20 | PLL Post Divider | PLL Postdivision |
24 | sdRamConfig | SDRAM Configuration Register |
28 | Refresh ctl | SDRAM Refresh Control Register |
32 | Timing 1 | SDRAM Timing 1 Register |
36 | Timing 2 | SDRAM Timing 2 Register |
40 | Timing 3 | SDRAM Timing 3 Register |
44 | Timing4 | SDRAM Timing 4 Register |
48 | Pwr management | Power Management Control Register |
52 | Vbus M cfg | VBUS M Configuration |
56 | Vbus M cfg val 1 | VBUS M Configuration Value 1 |
60 | Vbus M cfg val 2 | VBUSM Configuration Value 2 |
64 | IO DFT Test | I/O DFT test logic control |
68 | Perf ctl sel | Performance Counter Master Region Select Register |
72 | Perf cnt Mst Reg | Performance Count Master Region Select |
76 | Zq config | SDRAM Output Impedance Calibration Configuration Register |
80 | Pri Class Svc Map | Priority class Service Map |
84 | Mst Id class 1 | Master ID class service map 1 |
88 | Mst Id class 2 | Master ID class service map 2 |
92 | ECC ctrl | ECC Control Register |
96 | ECC addr rng 1 | ECC Address Range 1 Register |
100 | ECC addr rng 2 | ECC Address Range 2 Register |
104 | Rw/exc thresh | Read Write Execution Threshold Register |
108 | PHY PIR | PHY PIR register (SLSW mask bit 0) |
112 | PHY PGCR0 | PHY PGCR0 register (SLSW mask bit 1) |
116 | PHY PGCR1 | PHY PGCR1 register (SLSW mask bit 2) |
120 | PHY PGCR2 | PHY PGCR2 register (SLSW mask bit 3) |
124 | PHY PGSR0 | PHY PGSR0 register (SLSW mask bit 4) |
128 | PHY PGSR1 | PHY PGSR1 register (SLSW mask bit 5) |
132 | PHY PTR0 | PHY PTR 0 register (SLSW mask bit 6) |
136 | PHY PTR1 | PHY PTR 1 register (SLSW mask bit 7) |
140 | PHY PTR2 | PHY PTR 2 register (SLSW mask bit 8) |
144 | PHY PTR3 | PHY PTR 3 register (SLSW mask bit 9) |
148 | PHY PTR4 | PHY PTR 4 register (SLSW mask bit 10) |
152 | PHY DCR | PHY DCR register (SLSW mask bit 11) |
156 | PHY DTPR0 | PHY DTPR 0 register (SLSW mask bit 12) |
160 | PHY DTPR1 | PHY DTPR 1 register (SLSW mask bit 13) |
164 | PHY DTPR2 | PHY DTPR 2 register (SLSW mask bit 14) |
168 | PHY MR0 | PHY MR 0 register (SLSW mask bit 15) |
172 | PHY MR1 | PHY MR 1 register (SLSW mask bit 16) |
176 | PHY MR2 | PHY MR 2 register (SLSW mask bit 17) |
180 | PHY DTCR | PHY DTCR register (SLSW mask bit 18) |
184 | PHY DX0GCR | PHY DX 0 GCR register (SLSW mask bit 19) |
188 | PHY DX1GCR | PHY DX 1 GCR register (SLSW mask bit 20) |
192 | PHY DX2GCR | PHY DX 2 GCR register (SLSW mask bit 21) |
196 | PHY DX3GCR | PHY DX 3 GCR register (SLSW mask bit 22) |
200 | PHY DX4CGR | PHY DX 4 GCR register (SLSW mask bit 23) |
204 | PHY DX5GCR | PHY DX 5 GCR register (SLSW mask bit 24) |
208 | PHY DX6GCR | PHY DX 6 GCR register (SLSW mask bit 25) |
212 | PHY DX7GCR | PHY DX 7 GCR register (SLSW mask bit 26) |
216 | PHY DX8GCR | PHY DX 8 GCR register (SLSW mask bit 27) |