ZHCSBT2G November 2012 – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14
PRODUCTION DATA.
The registers defined in ARM Configuration register 1 (ARMENDIAN_CFGr_1) control the way Cortex-A15 processor core access to peripheral MMRs shows up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant view of the peripheral MMRs when performing a 32-bit access. (Only one of the eight register sets is shown in Figure 10-32 and described in Table 10-51.)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SIZE | ||||||||||||||||||||||||||||||
R-0000 0000 0000 0000 0000 0000 0000 | RW-0000 |
Legend: RW = Read/Write; R = Read only |
Bit | Field | Description |
---|---|---|
31-4 | Reserved | Reserved |
3-0 | SIZE | 4-bit encoded size of Configuration Region R
The value in the SIZE field defines the size of the contiguous block of memory-mapped register space for which a word swap is done by the ARM CorePac bridge (starting from ARMENDIAN_CFGr_0.BASEADDR).
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