ZHCSBT2G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
      1. 1.3.1 KeyStone II 的增强功能
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. 6 C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
      1. Table 6-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    7. 6.7 C66x CorePac Register Descriptions
  7. 7 ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. 8 Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
            1. Table 8-9 Configuration Register Field Descriptions
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 8-10 Programmable Range n Start Address Register Field Descriptions
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
          1. Table 8-14 Programmable Range n End Address Register Field Descriptions
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
          1. Table 8-18 Programmable Range n Memory Protection Page Attribute Register Field Descriptions
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
          1. Table 10-3 Boot Mode Pins: Boot Device Values
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
            1. Table 10-4 Sleep Boot Configuration Field Descriptions
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
              1. Table 10-5 I2C Passive Mode Device Configuration Field Descriptions
            2. 10.1.2.2.2.2 I2C Master Mode
              1. Table 10-6 I2C Master Mode Device Configuration Field Descriptions
          3. 10.1.2.2.3 SPI Boot Device Configuration
            1. Table 10-7 SPI Device Configuration Field Descriptions
          4. 10.1.2.2.4 EMIF Boot Device Configuration
            1. Table 10-8 EMIF Boot Device Configuration Field Descriptions
          5. 10.1.2.2.5 NAND Boot Device Configuration
            1. Table 10-9 NAND Boot Device Configuration Field Descriptions
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
          1. Table 10-10 Serial Rapid I/O Boot Device Configuration Field Descriptions
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. Table 10-11 Ethernet (SGMII) Boot Device Configuration Field Descriptions
          2. 10.1.2.4.1   PCIe Boot Device Configuration
            1. Table 10-12 PCIe Boot Device Configuration Field Descriptions
          3. 10.1.2.4.2   HyperLink Boot Device Configuration
            1. Table 10-14 HyperLink Boot Device Configuration Field Descriptions
          4. 10.1.2.4.3   UART Boot Device Configuration
            1. Table 10-15 UART Boot Configuration Field Descriptions
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
          1. Table 10-31 Device Status Register Field Descriptions
        2. 10.2.3.2  Device Configuration Register
          1. Table 10-32 Device Configuration Register Field Descriptions
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
          1. Table 10-33 JTAG ID Register Field Descriptions
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
          1. Table 10-1 DSP BOOT Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
          1. Table 10-35 LRESETNMI PIN Status Register Field Descriptions
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
          1. Table 10-36 LRESETNMI PIN Status Clear Register Field Descriptions
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
          1. Table 10-37 Reset Status Register Field Descriptions
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
          1. Table 10-38 Reset Status Clear Register Field Descriptions
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
          1. Table 10-39 Boot Complete Register Field Descriptions
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
          1. Table 10-40 Power State Control Register Field Descriptions
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
          1. Table 10-41 NMI Generation Register Field Descriptions
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
          1. Table 10-42 IPC Generation Registers Field Descriptions
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
          1. Table 10-43 IPC Acknowledgment Registers Field Descriptions
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
          1. Table 10-44 IPC Generation Registers Field Descriptions
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
          1. Table 10-45 IPC Acknowledgment Register Field Descriptions
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
          1. Table 10-46 Timer Input Selection Field Description
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
          1. Table 10-47 Timer Output Selection Register Field Descriptions
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
          1. Table 10-48 Reset Mux Register Field Descriptions
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
          1. Table 10-49 Device Speed Register Field Descriptions
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
          1. Table 10-50 ARM Endian Configuration Register 0 Field Descriptions
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
          1. Table 10-51 ARM Endian Configuration Register 1 Field Descriptions
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
          1. Table 10-52 ARM Endian Configuration Register 2 Field Descriptions
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
          1. Table 10-53 Chip Miscellaneous Control Register Field Descriptions
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
          1. Table 10-54 Chip Miscellaneous Control Register Field Descriptions
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
          1. Table 10-55 System Endian Status Register Field Descriptions
        27. 10.2.3.27 SYNECLK_PINCTL Register
          1. Table 10-56 SYNECLK_PINCTL Register Field Descriptions
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
          1. Table 10-57 USB_PHY_CTL0 Register Field Descriptions
          2. Table 10-58 USB_PHY_CTL1 Register Field Descriptions
          3. Table 10-59 USB_PHY_CTL2 Register Field Descriptions
          4. Table 10-60 USB_PHY_CTL3 Register Field Descriptions
          5. Table 10-61 USB_PHY_CTL4 Register Field Descriptions
          6. Table 10-62 USB_PHY_CTL5 Register Field Descriptions
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
        1. Table 11-5 SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
        1. Table 11-10 Reset Timing Requirements
        2. Table 11-11 Reset Switching Characteristics
        3. Table 11-12 Boot Configuration Timing Requirements
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 11-16 PLL Secondary Control Register Field Descriptions
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
          1. Table 11-17 PLL Controller Divider Register Field Descriptions
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 11-18 PLL Controller Clock Align Control Register Field Descriptions
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 11-19 PLLDIV Divider Ratio Change Status Register Field Descriptions
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 11-20 SYSCLK Status Register Field Descriptions
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 11-21 Reset Type Status Register Field Descriptions
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 11-22 Reset Control Register Field Descriptions
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 11-23 Reset Configuration Register Field Descriptions
        9. 11.5.2.9 Reset Isolation Register (RSISO)
          1. Table 11-24 Reset Isolation Register Field Descriptions
      3. 11.5.3 Main PLL Control Registers
        1. Table 11-25 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 11-26 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 11.5.4 ARM PLL Control Registers
        1. Table 11-27 ARM PLL Control Register 0 Field Descriptions
        2. Table 11-28 ARM PLL Control Register 1 Field Descriptions
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
        1. Table 11-29 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Timing Requirements
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
        1. Table 11-30 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions
        2. Table 11-31 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
        1. Table 11-32 DDR3 PLL DDRCLK(N|P) Timing Requirements
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
        1. Table 11-33 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0)
        2. Table 11-34 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1)
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
        1. Table 11-35 PASS PLL Timing Requirements
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
        1. Table 11-36 NMI and LRESET Timing Requirements
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
        1. Table 11-38 I2C Timing Requirements
        2. Table 11-39 I2C Switching Characteristics
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
        1. Table 11-40 SPI Timing Requirements
        2. Table 11-41 SPI Switching Characteristics
    12. 11.12 HyperLink Peripheral
      1. Table 11-42 HyperLink Peripheral Timing Requirements
      2. Table 11-43 HyperLink Peripheral Switching Characteristics
    13. 11.13 UART Peripheral
      1. Table 11-44 UART Timing Requirements
      2. Table 11-45 UART Switching Characteristics
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
      1. Table 11-46 MACID1 Register Field Descriptions
      2. Table 11-47 MACID2 Register Field Descriptions
      3. Table 11-48 RFTCLK Select Register Field Descriptions
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
      1. Table 11-49 MDIO Timing Requirements
      2. Table 11-50 MDIO Switching Characteristics
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
        1. Table 11-51 Timer Input Timing Requirements
        2. Table 11-52 Timer Output Switching Characteristics
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
        1. Table 11-54 GPIO Input Timing Requirements
        2. Table 11-55 GPIO Output Switching Characteristics
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
        1. Table 11-56 EMIF16 Asynchronous Memory Timing Requirements
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
          1. Table 11-66 Trace Switching Characteristics
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
          1. Table 11-67 JTAG Test Port Timing Requirements
          2. Table 11-68 JTAG Test Port Switching Characteristics
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

封装选项

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机械数据 (封装 | 引脚)
  • AAW|1517
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.2.3 CIC2 Register Map

Table 8-29 CIC2 Registers

ADDRESS OFFSET REGISTER MNEMONIC REGISTER NAME
0x0 REVISION_REG Revision Register
0x10 GLOBAL_ENABLE_HINT_REG Global Host Int Enable Register
0x20 STATUS_SET_INDEX_REG Status Set Index Register
0x24 STATUS_CLR_INDEX_REG Status Clear Index Register
0x28 ENABLE_SET_INDEX_REG Enable Set Index Register
0x2C ENABLE_CLR_INDEX_REG Enable Clear Index Register
0x34 HINT_ENABLE_SET_INDEX_REG Host Int Enable Set Index Register
0x38 HINT_ENABLE_CLR_INDEX_REG Host Int Enable Clear Index Register
0x200 RAW_STATUS_REG0 Raw Status Register 0
0x204 RAW_STATUS_REG1 Raw Status Register 1
0x208 RAW_STATUS_REG2 Raw Status Register 2
0x20C RAW_STATUS_REG3 Raw Status Register 3
0x210 RAW_STATUS_REG4 Raw Status Register 4
0x214 RAW_STATUS_REG5 Raw Status Register 5
0x218 RAW_STATUS_REG6 Raw Status Register 6
0x21C RAW_STATUS_REG7 Raw Status Register 7
0x220 RAW_STATUS_REG8 Raw Status Register 8
0x224 RAW_STATUS_REG9 Raw Status Register 9
0x228 RAW_STATUS_REG10 Raw Status Register 10
0x22C RAW_STATUS_REG11 Raw Status Register 11
0x230 RAW_STATUS_REG12 Raw Status Register 12
0x234 RAW_STATUS_REG13 Raw Status Register 13
0x238 RAW_STATUS_REG14 Raw Status Register 14
0x23C RAW_STATUS_REG15 Raw Status Register 15
0x280 ENA_STATUS_REG0 Enabled Status Register 0
0x284 ENA_STATUS_REG1 Enabled Status Register 1
0x288 ENA_STATUS_REG2 Enabled Status Register 2
0x28C ENA_STATUS_REG3 Enabled Status Register 3
0x290 ENA_STATUS_REG4 Enabled Status Register 4
0x294 ENA_STATUS_REG5 Enabled Status Register 5
0x298 ENA_STATUS_REG6 Enabled Status Register 6
0x29C ENA_STATUS_REG7 Enabled Status Register 7
0x2A0 ENA_STATUS_REG8 Enabled Status Register 8
0x2A4 ENA_STATUS_REG9 Enabled Status Register 9
0x2A8 ENA_STATUS_REG10 Enabled Status Register10
0x2AC ENA_STATUS_REG11 Enabled Status Register 11
0x2B0 ENA_STATUS_REG12 Enabled Status Register 12
0x2B4 ENA_STATUS_REG13 Enabled Status Register 13
0x2B8 ENA_STATUS_REG14 Enabled Status Register 14
0x2BC ENA_STATUS_REG15 Enabled Status Register 15
0x300 ENABLE_REG0 Enable Register 0
0x304 ENABLE_REG1 Enable Register 1
0x308 ENABLE_REG2 Enable Register 2
0x30C ENABLE_REG3 Enable Register 3
0x310 ENABLE_REG4 Enable Register 4
0x314 ENABLE_REG5 Enable Register 5
0x318 ENABLE_REG6 Enable Register 6
0x31C ENABLE_REG7 Enable Register 7
0x320 ENABLE_REG8 Enable Register 8
0x324 ENABLE_REG9 Enable Register 9
0x328 ENABLE_REG10 Enable Register 10
0x32C ENABLE_REG11 Enable Register 11
0x330 ENABLE_REG12 Enable Register 12
0x334 ENABLE_REG13 Enable Register 13
0x338 ENABLE_REG14 Enable Register 14
0x33C ENABLE_REG15 Enable Register 15
0x380 ENABLE_CLR_REG0 Enable Clear Register 0
0x384 ENABLE_CLR_REG1 Enable Clear Register 1
0x388 ENABLE_CLR_REG2 Enable Clear Register 2
0x38C ENABLE_CLR_REG3 Enable Clear Register 3
0x390 ENABLE_CLR_REG4 Enable Clear Register 4
0x394 ENABLE_CLR_REG5 Enable Clear Register 5
0x398 ENABLE_CLR_REG6 Enable Clear Register 6
0x39C ENABLE_CLR_REG7 Enable Clear Register 7
0x3A0 ENABLE_CLR_REG8 Enable Clear Register 8
0x3A4 ENABLE_CLR_REG9 Enable Clear Register 9
0x3A8 ENABLE_CLR_REG10 Enable Clear Register 10
0x3AC ENABLE_CLR_REG11 Enable Clear Register 11
0x3B0 ENABLE_CLR_REG12 Enable Clear Register 12
0x3B4 ENABLE_CLR_REG13 Enable Clear Register 13
0x3B8 ENABLE_CLR_REG14 Enable Clear Register 14
0x38C ENABLE_CLR_REG15 Enable Clear Register 15
0x400 CH_MAP_REG0 Interrupt Channel Map Register for 0 to 0+3
0x404 CH_MAP_REG1 Interrupt Channel Map Register for 4 to 4+3
0x408 CH_MAP_REG2 Interrupt Channel Map Register for 8 to 8+3
0x40C CH_MAP_REG3 Interrupt Channel Map Register for 12 to 12+3
0x410 CH_MAP_REG4 Interrupt Channel Map Register for 16 to 16+3
0x414 CH_MAP_REG5 Interrupt Channel Map Register for 20 to 20+3
0x418 CH_MAP_REG6 Interrupt Channel Map Register for 24 to 24+3
0x41C CH_MAP_REG7 Interrupt Channel Map Register for 28 to 28+3
0x420 CH_MAP_REG8 Interrupt Channel Map Register for 32 to 32+3
0x424 CH_MAP_REG9 Interrupt Channel Map Register for 36 to 36+3
0x428 CH_MAP_REG10 Interrupt Channel Map Register for 40 to 40+3
0x42C CH_MAP_REG11 Interrupt Channel Map Register for 44 to 44+3
0x430 CH_MAP_REG12 Interrupt Channel Map Register for 48 to 48+3
0x434 CH_MAP_REG13 Interrupt Channel Map Register for 52 to 52+3
0x438 CH_MAP_REG14 Interrupt Channel Map Register for 56 to 56+3
0x43C CH_MAP_REG15 Interrupt Channel Map Register for 60 to 60+3
0x5C0 CH_MAP_REG116 Interrupt Channel Map Register for 464 to 464+3
0x5C4 CH_MAP_REG117 Interrupt Channel Map Register for 468 to 468+3
0x5C8 CH_MAP_REG118 Interrupt Channel Map Register for 472 to 472+3
0x5CC CH_MAP_REG119 Interrupt Channel Map Register for 476 to 476+3
0x5D0 CH_MAP_REG120 Interrupt Channel Map Register for 480 to 480+3
0x5D4 CH_MAP_REG121 Interrupt Channel Map Register for 484 to 484+3
0x5D8 CH_MAP_REG122 Interrupt Channel Map Register for 488 to 488+3
0x5DC CH_MAP_REG123 Interrupt Channel Map Register for 482 to 492+3
0x5E0 CH_MAP_REG124 Interrupt Channel Map Register for 496 to 496+3
0x5E4 CH_MAP_REG125 Interrupt Channel Map Register for 500 to 500+3
0x5E8 CH_MAP_REG126 Interrupt Channel Map Register for 504 to 504+3
0x5EC CH_MAP_REG127 Interrupt Channel Map Register for 508 to 508+3
0x5F0 CH_MAP_REG128 Interrupt Channel Map Register for 512 to 512+3
0x5F4 CH_MAP_REG129 Interrupt Channel Map Register for 516 to 516+3
0x5F8 CH_MAP_REG130 Interrupt Channel Map Register for 520 to 520+3
0x5FC CH_MAP_REG131 Interrupt Channel Map Register for 524 to 524+3
0x600 CH_MAP_REG132 Interrupt Channel Map Register for 528 to 528+3
0x604 CH_MAP_REG133 Interrupt Channel Map Register for 532 to 532+3
0x608 CH_MAP_REG134 Interrupt Channel Map Register for 536 to 536+3
0x60C CH_MAP_REG135 Interrupt Channel Map Register for 540 to 540+3
0x610 CH_MAP_REG136 Interrupt Channel Map Register for 544 to 544+3
0x614 CH_MAP_REG137 Interrupt Channel Map Register for 548 to 548+3
0x618 CH_MAP_REG138 Interrupt Channel Map Register for 552 to 552+3
0x61C CH_MAP_REG139 Interrupt Channel Map Register for 556 to 556+3
0x620 CH_MAP_REG140 Interrupt Channel Map Register for 560 to 560+3
0x624 CH_MAP_REG141 Interrupt Channel Map Register for 564 to 564+3
0x628 CH_MAP_REG142 Interrupt Channel Map Register for 568 to 568+3
0x62C CH_MAP_REG143 Interrupt Channel Map Register for 572 to 572+3
0x630 CH_MAP_REG144 Interrupt Channel Map Register for 576 to 576+3
0x634 CH_MAP_REG145 Interrupt Channel Map Register for 580 to 580+3
0x638 CH_MAP_REG146 Interrupt Channel Map Register for 584 to 584+3
0x63C CH_MAP_REG147 Interrupt Channel Map Register for 588 to 588+3
0x640 CH_MAP_REG148 Interrupt Channel Map Register for 592 to 592+3
0x644 CH_MAP_REG149 Interrupt Channel Map Register for 596 to 596+3
0x648 CH_MAP_REG150 Interrupt Channel Map Register for 600 to 600+3
0x64C CH_MAP_REG151 Interrupt Channel Map Register for 604 to 604+3
0x650 CH_MAP_REG152 Interrupt Channel Map Register for 608 to 608+3
0x654 CH_MAP_REG153 Interrupt Channel Map Register for 612 to 612+3
0x658 CH_MAP_REG154 Interrupt Channel Map Register for 616 to 616+3
0x65C CH_MAP_REG155 Interrupt Channel Map Register for 620 to 620+3
0x660 CH_MAP_REG156 Interrupt Channel Map Register for 624 to 624+3
0x664 CH_MAP_REG157 Interrupt Channel Map Register for 628 to 628+3
0x668 CH_MAP_REG158 Interrupt Channel Map Register for 632 to 632+3
0x66C CH_MAP_REG159 Interrupt Channel Map Register for 636 to 636+3
0x670 CH_MAP_REG160 Interrupt Channel Map Register for 640 to 640+3
0x674 CH_MAP_REG161 Interrupt Channel Map Register for 644 to 644+3
0x678 CH_MAP_REG162 Interrupt Channel Map Register for 648 to 648+3
0x67C CH_MAP_REG163 Interrupt Channel Map Register for 652 to 652+3
0x680 CH_MAP_REG164 Interrupt Channel Map Register for 656 to 656+3
0x684 CH_MAP_REG165 Interrupt Channel Map Register for 660 to 660+3
0x688 CH_MAP_REG166 Interrupt Channel Map Register for 664 to 664+3
0x68C CH_MAP_REG167 Interrupt Channel Map Register for 668 to 668+3
0x690 CH_MAP_REG168 Interrupt Channel Map Register for 672 to 672+3
0x694 CH_MAP_REG169 Interrupt Channel Map Register for 676 to 676+3
0x698 CH_MAP_REG170 Interrupt Channel Map Register for 680 to 680+3
0x69C CH_MAP_REG171 Interrupt Channel Map Register for 684 to 684+3
0x800 HINT_MAP_REG0 Host Interrupt Map Register for 0 to 0+3
0x804 HINT_MAP_REG1 Host Interrupt Map Register for 4 to 4+3
0x808 HINT_MAP_REG2 Host Interrupt Map Register for 8 to 8+3
0x80C HINT_MAP_REG3 Host Interrupt Map Register for 12 to 12+3
0x810 HINT_MAP_REG4 Host Interrupt Map Register for 16 to 16+3
0x814 HINT_MAP_REG5 Host Interrupt Map Register for 20 to 20+3
0x818 HINT_MAP_REG6 Host Interrupt Map Register for 24 to 24+3
0x81C HINT_MAP_REG7 Host Interrupt Map Register for 28 to 28+3
0x820 HINT_MAP_REG8 Host Interrupt Map Register for 32 to 32+3
0x824 HINT_MAP_REG9 Host Interrupt Map Register for 36 to 36+3
0x828 HINT_MAP_REG10 Host Interrupt Map Register for 40 to 40+3
0x82C HINT_MAP_REG11 Host Interrupt Map Register for 44 to 44+3
0x830 HINT_MAP_REG12 Host Interrupt Map Register for 48 to 48+3
0x834 HINT_MAP_REG13 Host Interrupt Map Register for 52 to 52+3
0x838 HINT_MAP_REG14 Host Interrupt Map Register for 56 to 56+3
0x83C HINT_MAP_REG15 Host Interrupt Map Register for 60 to 60+3
0x840 HINT_MAP_REG16 Host Interrupt Map Register for 63 to 63+3
0x844 HINT_MAP_REG17 Host Interrupt Map Register for 66 to 66+3
0x848 HINT_MAP_REG18 Host Interrupt Map Register for 68 to 68+3
0x84C HINT_MAP_REG19 Host Interrupt Map Register for 72 to 72+3
0x850 HINT_MAP_REG20 Host Interrupt Map Register for 76 to 76+3
0x854 HINT_MAP_REG21 Host Interrupt Map Register for 80 to 80+3
0x858 HINT_MAP_REG22 Host Interrupt Map Register for 84 to 84+3
0x85C HINT_MAP_REG23 Host Interrupt Map Register for 88 to 88+3
0x860 HINT_MAP_REG24 Host Interrupt Map Register for 92 to 92+3
0x864 HINT_MAP_REG25 Host Interrupt Map Register for 94 to 94+3
0x868 HINT_MAP_REG26 Host Interrupt Map Register for 96 to 96+3
0x86C HINT_MAP_REG27 Host Interrupt Map Register for 100 to 100+3
0x1500 ENABLE_HINT_REG0 Host Int Enable Register 0
0x1504 ENABLE_HINT_REG1 Host Int Enable Register 1