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TMS320C6655

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高性能单核 C66x 定点和浮点 DSP- 高达 1.25GHz

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TMS320C6655

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产品详情

CPU 32-/64-bit Frequency (MHz) 1000, 1250 PCIe 2 PCIe Gen2 Hardware accelerators TCP3d, VCP2 Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 100
CPU 32-/64-bit Frequency (MHz) 1000, 1250 PCIe 2 PCIe Gen2 Hardware accelerators TCP3d, VCP2 Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (GZH) 625 441 mm² (21 mm × 21 mm) FCBGA (CZH) 625 441 mm² (21 mm × 21 mm)
  • One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
    • 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core
      • 40 GMAC per Core for Fixed Point @ 1.25 GHz
      • 20 GFLOP per Core for Floating Point @ 1.25 GHz
  • Multicore Shared Memory Controller (MSMC)
    • 1024KB MSM SRAM Memory
      (Shared by Two DSP C66x CorePacs for C6657)
    • Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Hardware Accelerators
    • Two Viterbi Coprocessors
    • One Turbo Coprocessor Decoder
  • Peripherals
    • Four Lanes of SRIO 2.1
      • 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane
      • Supports Direct I/O, Message Passing
      • Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
    • PCIe Gen2
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • HyperLink
      • Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
      • Supports up to 40 Gbaud
    • Gigabit Ethernet (GbE) Subsystem
      • One SGMII Port
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1333
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Up to Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C
  • One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
    • 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core
      • 40 GMAC per Core for Fixed Point @ 1.25 GHz
      • 20 GFLOP per Core for Floating Point @ 1.25 GHz
  • Multicore Shared Memory Controller (MSMC)
    • 1024KB MSM SRAM Memory
      (Shared by Two DSP C66x CorePacs for C6657)
    • Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Hardware Accelerators
    • Two Viterbi Coprocessors
    • One Turbo Coprocessor Decoder
  • Peripherals
    • Four Lanes of SRIO 2.1
      • 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane
      • Supports Direct I/O, Message Passing
      • Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
    • PCIe Gen2
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • HyperLink
      • Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
      • Supports up to 40 Gbaud
    • Gigabit Ethernet (GbE) Subsystem
      • One SGMII Port
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1333
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Up to Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C

The C665x are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, both C665x DSPs enable a platform that is power-efficient and easy to use. In addition, the C665x DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 40 GMACS per core and 20 GFLOPS per core (@1.25 GHz operating frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C665x DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1333 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink is included.

The C665x devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that lets SoCs work in tandem. The low-protocol overhead and high throughput of HyperLink make an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

The C665x are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, both C665x DSPs enable a platform that is power-efficient and easy to use. In addition, the C665x DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 40 GMACS per core and 20 GFLOPS per core (@1.25 GHz operating frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C665x DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1333 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink is included.

The C665x devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that lets SoCs work in tandem. The low-protocol overhead and high throughput of HyperLink make an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor 数据表 (Rev. D) PDF | HTML 2019-9-4
* 勘误表 TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C) 2016-5-19
应用手册 DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022-7-7
应用手册 KeyStone 错误检测和校正 (Rev. A) PDF | HTML 英语版 (Rev.A) 2021-8-4
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 英语版 (Rev.A) PDF | HTML 2021-5-19
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020-6-1
应用手册 Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019-6-11
应用手册 Keystone Bootloader Resources and FAQ 2019-5-29
应用手册 Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019-5-17
应用手册 Hardware Design Guide for KeyStone Devices (Rev. D) PDF | HTML 2019-3-21
应用手册 KeyStone I DDR3 interface bring-up PDF | HTML 2019-3-6
应用手册 Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017-8-14
用户指南 Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017-7-26
应用手册 KeyStone I DDR3 Initialization (Rev. E) 2016-10-28
产品概述 TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A) 2016-5-23
应用手册 SERDES Link Commissioning on KeyStone I and II Devices 2016-4-13
应用手册 TI DSP Benchmarking PDF | HTML 2016-1-13
应用手册 Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015-8-13
用户指南 Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML 2015-5-6
用户指南 Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015-4-9
白皮书 TI’s processors leading the way in embedded analytics 2015-3-3
用户指南 DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E) 2015-1-20
应用手册 TI Keystone DSP PCIe SerDes IBIS-AMI Models 2014-10-9
应用手册 TI Keystone DSP Hyperlink SerDes IBIS-AMI Models 2014-10-9
用户指南 Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014-9-4
用户指南 Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) 2014-9-3
更多文献资料 KeyStone Lab Manual - Training 2014-6-5
用户指南 System Analyzer User's Guide (Rev. F) 2013-11-18
用户指南 PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 2013-9-30
用户指南 DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013-7-15
白皮书 Accelerating high-performance computing development with Desktop Linux SDK 2013-7-8
用户指南 Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013-6-28
用户指南 C66x CorePac User's Guide (Rev. C) 2013-6-28
用户指南 HyperLink for KeyStone Devices User's Guide (Rev. C) 2013-5-28
产品概述 OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) 2012-11-5
应用手册 SerDes Implementation Guidelines for KeyStone I Devices 2012-10-31
产品概述 TMS320C66x high-performance multicore DSPs for video surveillance 2012-9-6
应用手册 Multicore Programming Guide (Rev. B) 2012-8-29
用户指南 TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 2012-8-21
用户指南 TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 2012-8-21
用户指南 Ethernet Media Access Controller (EMAC) User's Guide for KeyStone Devices 2012-7-12
用户指南 Universal Parallel Port (uPP) for KeyStone Architecture User's Guide 2012-6-11
用户指南 Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices 2012-5-25
白皮书 Leveraging multicore processors for machine vision applications 2012-5-9
用户指南 Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012-3-30
用户指南 Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012-3-27
白皮书 Superior performance at breakthrough size, weight & power 2012-3-26
用户指南 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012-3-22
白皮书 Maximizing Multicore Efficiency with Navigator Runtime 2012-2-23
应用手册 PCIe Use Cases for KeyStone Devices 2011-12-13
用户指南 Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A) 2011-10-15
应用手册 Introduction to TMS320C6000 DSP Optimization 2011-10-6
用户指南 Debug and Trace for KeyStone I Devices User's Guide (Rev. A) 2011-9-22
用户指南 Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011-9-2
白皮书 KeyStone Multicore SoC Tool Suite: one platform for all needs 2011-6-17
用户指南 Viterbi-Decoder Coprocessor 2 (VCP2) for KeyStone Devices User's Guide (Rev. A) 2011-6-10
用户指南 External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011-5-24
白皮书 Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011-5-19
应用手册 TMS320C66x DSP Generation of Devices (Rev. A) 2011-4-25
白皮书 Software-Based Ultrasound Phase Rotation Beamforming on Multicore DSP 2011-3-16
白皮书 Software-Based Ultrasound Beamforming on Multicore DSPs 2011-3-6
白皮书 “KeyStone Memory Architecture”（梯形存储器架构）白皮书 (Rev. A) 2010-12-21
用户指南 Turbo Decoder Coprocessor 3 (TCP3D) for KeyStone Devices User's Guide 2010-11-18
应用手册 Optimizing Loops on the C66x DSP 2010-11-9
用户指南 General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010-11-9
用户指南 C66x CPU and Instruction Set Reference Guide 2010-11-9
应用手册 Clocking Design Guide for KeyStone Devices 2010-11-9
用户指南 Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010-11-9
用户指南 C66x DSP Cache User's Guide 2010-11-9
用户指南 Flip Chip Ball Grid Array Package Reference Guide (Rev. A) 2005-5-23
应用手册 AN-1281 Bumped Die (Flip Chip) Packages (Rev. A) 2004-5-1

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

TMDSEVM6657 — TMS320C6657 Lite 评估模块

TMS320C6657LS Lite 评估模块 (EVM) 是易于使用且符合成本效益的开发工具，可帮助开发人员使用 C6657、C6655 或 C6654 系列 DSP 快速着手进行设计。EVM 包括具有强大连接选项的单个板载 C6657 处理器，使客户可以在各种系统中使用此 AMC 封装卡。它还可用作独立电路板。随附 6657LS EVM 的软件包括 Code Composer Studio™ 集成开发环境版本 5 (CCS v5)、包含板级支持包 (BSP) 的 TI 多核软件开发套件 (MCSDK)、芯片支持库 (CSL)、加电自检测 (POST)、网络开发套件 (...)

支持的产品和硬件
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限制：
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无货
子卡

SHELD-3P-DSP-SOMS — Sheldon DSP-FPGA 电路板

Sheldon Instruments 为 PCIe/PCI、PCI104e/PCI104、XMC/PMC 和 CompactPCI 系统设计和制造基于 DSP 的 COTS 数据采集和控制硬件，以及适用于各种应用和市场的驱动程序和实时开发软件。

如需了解有关 Sheldon 仪器的更多信息，请访问 https://sheldoninstruments.com。




来源：Sheldon Instruments, Inc.
支持的产品和硬件
调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针（仿真器）。对于大多数器件，建议使用较新、成本较低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 在单个仓体中支持更广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。

XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 引脚的多个适配器）连接到目标板，并通过 USB2.0 高速 (...)

支持的产品和硬件
有库存
限制：
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无货
调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。  请注意，它不支持串行线调试 (SWD)。

对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS 调试探针均支持核心和系统跟踪。  对于引脚上的跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

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有库存
限制：
??asset.out-of-stock-ti_zh_CN??
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调试探针

LB-3P-TRACE32-DSP — 适用于数字信号处理器 (DSP) 的 Lauterbach TRACE32 调试和跟踪系统

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

来源：Lauterbach GmbH
支持的产品和硬件
软件开发套件 (SDK)

PROCESSOR-SDK-C665X — 适用于 C665x 处理器的处理器 SDK – TI-RTOS 支持

Processor SDK（软件开发套件）是统一的软件平台，适用于 TI 嵌入式处理器，设置简单，提供开箱即用的快速基准测试和演示。  Processor SDK 的所有版本在 TI 的广泛产品系列中保持一致，让开发人员可以无缝地在多种器件之间重用和迁移软件。  借助 Processor SDK 和 TI 的嵌入式处理器解决方案，开发可扩展平台解决方案从未如此简单。

适用于 C66x 的处理器 SDK v.02.xx 包括对 TI-RTOS 操作系统的支持。

RTOS 亮点：

  • TI-RTOS 内核，适用于 TI 器件的轻量级实时嵌入式操作系统
  • 芯片支持库、驱动程序和基本的板级支持实用程序
  • (...)
支持的产品和硬件
IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

支持的产品和硬件
驱动程序或库

MATHLIB — 用于浮点器件的 DSP 数学函数库

德州仪器 (TI) 数学库是优化的浮点数学函数库，用于使用 TI 浮点器件的 C 编程器。这些例程通常用于计算密集型实时应用，最佳执行速度是这些应用的关键。通过使用这些例程（而不是在现有运行时支持中找到的例程），您可以在无需重写现有代码的情况下获得更快的执行速度。MATHLIB 库包括目前在现有实时支持库中提供的所有浮点数学例程。这些新函数可称为当前实时支持库名称或包含在数学库中的新名称。
支持的产品和硬件
驱动程序或库

SPRC264 — TMS320C5000/6000 图像库 (IMGLIB)

C5000/6000 图像处理库 (IMGLIB) 是一款经过优化的图像/视频处理函数库，适用于 C 语言程序员。其中包括计算量庞大的实时应用程序常用的可使用 C 语言调用的通用影像/视频处理例程。使用这些例程可实现比等效标准 ANSI C 语言代码更高的性能。通过使用源代码提供即用型 DSP 函数，IMGLIB 可以显著缩短应用开发时间。

请参阅基准测试：DSP 内核基准测试

支持的产品和硬件
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 数字信号处理器库 (DSPLIB) 是一款平台优化型 DSP 函数库，适用于 C 编程器。它包括 C 语言可调用的通用信号处理例程，通常用于计算密集型的实时应用中。使用这些例程可实现比等效标准 ANSI C 语言代码更高的性能。通过使用源代码提供即用型 DSP 函数，DSPLIB 可以显著缩短应用开发时间。

请参阅基准测试：DSP 内核基准测试

支持的产品和硬件
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件
软件编解码器

C66XCODECS — 编解码器 - 视频和语音 – 用于基于 C66x 的设备

TI 编解码器免费提供，附带生产许可且现在可供下载。所有编解码器均经过生产环境测试，可轻松集成到视频和语音应用中。在许多情况下，我们会为 C66x 平台提供和验证 C64x+ 编解码器。下载页面及每个安装程序中都包含有数据表和发行说明。

通过点击下面的“下载选项”按钮获得的编解码器是 TI 当前提供的经过测试的最新版本。此外，某些应用演示也提供 TI 编解码器版本。演示中的编解码器版本不一定是最新版本。

支持的产品和硬件
仿真模型

C6655 Power Consumption Model

SPRM601.ZIP (176 KB) - 电源模型
支持的产品和硬件
仿真模型

KeyStone I SerDes IBIS AMI Models

SPRM742.ZIP (969314 KB) - IBIS 模型
lock = 需要出口许可（1 分钟）
支持的产品和硬件
仿真模型

TMS320C6655/57 CYP IBIS Model (revision 1.2)

SPRM570.ZIP (415 KB) - IBIS 模型
支持的产品和硬件
仿真模型

TMS320C6657/55/54 CZH BSDL Model (Silicon Revision 1)

SPRM572.ZIP (21 KB) - BSDL 模型
支持的产品和硬件
参考设计

TIDEP-0099 — 适用于语音应用的音频预处理系统参考设计

此参考设计采用多个麦克风、一个波束形成算法和其他处理器，可在噪声和其他杂波中提取清晰的语音和音频。  对于语音激活数字助理，在易产生噪音的环境中使用的应用数量快速增长，由此产生了对可以从嘈杂环境中提取清晰语音的系统的需求。  TIDEP-0099 参考设计采用麦克风阵列和精密的信号处理技术，可从嘈杂的环境中提取出清晰的音频。
支持的产品和硬件
参考设计

TIDEP0036 — 使用 TMS320C6657 实现高效 OPUS 编解码器解决方案的参考设计

TIDEP0036 参考设计提供了一个在 TMS320C6657 器件上轻松运行 TI 优化型 Opus 编码器/解码器的示例。由于 Opus 支持多种比特率、帧大小和采样率，所有这些都具有较低的延迟，因此它适用于语音通信、联网音频甚至高性能音频处理应用。   此设计还重点介绍了在 DSP 上实施 Opus 编解码器时与在 ARM 等通用处理器上实施 Opus 编解码器时所实现的性能改进。  根据常规用途处理器上运行的代码的优化级别，在 C66x TI DSP 内核上实现 Opus 编解码器的性能可以是 ARM CORTEX A-15 实现方案的 3 倍。TMS320C66x DSP (...)

支持的产品和硬件
参考设计

TIDEP0045 — 在 TI 的 C6678 DSP 上实现实时合成孔径雷达 (SAR) 算法的参考设计

该参考设计展示了在多核 TMS320C6678 数字信号处理器 (DSP) 上运行的实时合成孔径雷达 (SAR)。SAR 面临的主要挑战之一是实时生成高分辨率图像，因为形成这种图像会涉及到对计算有严格要求的信号处理流程。   我们已在 C6678 八核定点和浮点 DSP 上实现 SAR 算法，可为您展示完整的应用性能以及它如何跨单核、双核、四核及八核 DSP 进行扩展。这里从功能角度对距离多普勒 SAR 处理算法进行了模块化，并将计算任务映射到多个并行运行的内核。使用 OpenMP 来完成任务映射过程。

支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
FCBGA (GZH) 625 Ultra Librarian
FCBGA (CZH) 625 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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