产品详细信息

Sample rate (Max) (MSPS) 5200, 10400 Resolution (Bits) 8 Number of input channels 2, 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 8100 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.825 Power consumption (Typ) (mW) 3700 Architecture Folding Interpolating SNR (dB) 48.8 ENOB (Bits) 7.8 SFDR (dB) 65 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 5200, 10400 Resolution (Bits) 8 Number of input channels 2, 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 8100 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.825 Power consumption (Typ) (mW) 3700 Architecture Folding Interpolating SNR (dB) 48.8 ENOB (Bits) 7.8 SFDR (dB) 65 Operating temperature range (C) -40 to 85 Input buffer Yes
FCBGA (AAV) 144 100 mm² 10 x 10
  • ADC core:
    • 8-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –143.4 dBFS/Hz
      • Single-channel mode: –146.2 dBFS/Hz
    • ENOB (dual channel, FIN = 2.4 GHz, TYP): 7.8 Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.1 GHz
    • Usable input frequency range: > 10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Peak RF Input Power (Diff): +26.5 dBm (+ 27.5 dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 3.8 W
  • Power supplies: 1.1 V, 1.9 V
  • ADC core:
    • 8-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –143.4 dBFS/Hz
      • Single-channel mode: –146.2 dBFS/Hz
    • ENOB (dual channel, FIN = 2.4 GHz, TYP): 7.8 Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.1 GHz
    • Usable input frequency range: > 10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Peak RF Input Power (Diff): +26.5 dBm (+ 27.5 dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 3.8 W
  • Power supplies: 1.1 V, 1.9 V

The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10 GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. Support of a useable input frequency range of up to 10 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.

The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10 GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. Support of a useable input frequency range of up to 10 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.

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类型 标题 下载最新的英文版本 日期
* 数据表 ADC08DJ5200RF 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) 数据表 2018年 3月 8日
用户指南 ADCxxDJ5200RF Evaluation Module User's Guide (Rev. A) 2021年 6月 28日
技术文章 Keys to quick success using high-speed data converters 2020年 10月 13日
技术文章 How to achieve fast frequency hopping 2019年 3月 3日
技术文章 RF sampling: Learning more about latency 2017年 2月 9日
技术文章 Why phase noise matters in RF sampling converters 2016年 11月 28日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

评估板

ADC08DJ5200RFEVM — ADC08DJ5200RF 具有双通道 5.2GSPS 或单通道 10.4GSPS 的射频采样 8 位 ADC 评估模块

ADC08DJ5200RF 评估模块 (EVM) 是一款用于评估 ADC08DJ5200RF 的平台。ADC08DJ5200RF 是一款低功耗、8 位、双通道、5.2GSPS 或单通道 10.4GSPS RF 采样模数转换器 (ADC),具有缓冲模拟输入以及集成式数字降压转换器,采用 JESD204B/C 接口。该 EVM 具有变压器耦合模拟输入,可适应各种信号源和频率。

ADC08DJ5200RFEVM 中包含 LMX2594 时钟合成器和 LMK04828 JESD204B/C 时钟生成器,可以将其配置为超低抖动 ADC 器件时钟和 SYSREF,从而实现完整的 JESD204B/C 子类 (...)

现货
数量限制: 5
固件

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

JESD204 快速设计 IP 旨在为 FPGA 工程师提供一条快速通往运行中的 JESD204 系统的路径。该 IP 经过特别设计,可将下游数字处理和其他应用逻辑与 JESD204 协议的大多数性能和时序关键型限制因素隔离开。该 IP 将帮助设计人员节省固件开发时间并简化 FPGA 集成。

当您使用 TI 的高速数据转换器时,可免专利费使用 JESD204 快速设计 IP。TI 将协助用户配置初始链路,对其进行定制,以便在特定 FPGA 平台和 TI 数据转换器 JMODE 之间使用。在对该 IP 进行测试并确定其可以用于部署工作之后,TI 将会通过安全的下载链接提供该 IP。

JESD204 (...)

仿真工具

PSPICE-FOR-TI — PSPICE® for TI design and simulation tool

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。 

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
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FCBGA (AAV) 144 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

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