ZHCU831 November   2021 AWR2944

 

  1.   说明
  2.   资源
  3.   特性
  4.   应用
  5.   5
  6. 1System Description
    1. 1.1 Why use Radar?
    2. 1.2 TI Corner Radar Design
    3. 1.3 Key System Specification
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 AWR2944 Single-Chip Radar Solution
      2. 2.3.2 AWR2944 Evaluation Module
    4. 2.4 System Design Theory
      1. 2.4.1  Antenna Configuration
      2. 2.4.2  Chirp Configuration and System Performance
      3. 2.4.3  Data Path
      4. 2.4.4  Chirp Timing
      5. 2.4.5  eDMA Configuration
      6. 2.4.6  Memory Allocation
      7. 2.4.7  DDMA
      8. 2.4.8  Empty Subband Based DDMA
      9. 2.4.9  RANSAC
      10. 2.4.10 Group Tracker
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
      2. 3.1.2 Software and GUI
    2. 3.2 Test Setup
    3. 3.3 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 支持资源
    5. 4.5 Trademarks
  10. 5About the Author

2.4.6 Memory Allocation

The AWR2944 has the following memories:

  • DSS L3 RAM of 2.5MB (see Note)
  • DSS L2 RAM of 384KB
  • DSS L1D RAM of 32KB
  • DSS L1P RAM of 32KB
  • MSS L2 RAM of 960KB
Note:

L3 RAM for AWR2944 ES1.0: 2.25MB, ES2.0: 3MB.

Of the 32KB for L1P RAM and L1D RAM available, half (16KB) of the L1P RAM and half (16KB) of the L1D RAM are used as cache. The remaining half is reserved for code and data, and is unused.

DSS L2 RAM is used for:

  • Text section (code)
  • Data scratch buffers
  • DDMA Doppler FFT Demodulated submatrix
  • RTOS task stacks

DSS L3 RAM is used for:

  • Storing the compressed radarcube
  • Storing slices of decompressed radarcube for processing in scratch buffer
  • Object list

MSS L2 RAM is used for:

  • Text section (code)
  • Copying pointcloud in L3 produced by DSS. This allows DSS to work on next frame in parallel.
  • Converting between Cartesian and polar coordinate systems to interface with RANSAC and GTrack algorithms
  • Buffers for GTrack

Processing radar signals requires a large number of scratch buffers for each step of the processing stages. The available memory is used efficiently by overlaying the scratch buffers. A scratch buffer used in a previous stage can be re-used in the current stage. More details for this memory layout are found in the mmWave SDK documentation.