ZHCSH08 October   2017 MSP432E411Y

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 212-Pin ZAD (NFBGA) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. Table 5-3 Power and Brownout Levels
          2. 5.15.2.1.1 VDDA Levels
          3. 5.15.2.1.2 VDD Levels
          4. 5.15.2.1.3 VDDC Levels
          5. 5.15.2.1.4 VDD Glitch Response
          6. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
        1. Table 5-4 Reset Characteristics
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. Table 5-5 Phase Locked Loop (PLL) Characteristics
          2. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
          1. Table 5-9 Low-Frequency Oscillator Characteristics
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
          1. Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics
          2. Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics
        5. 5.15.4.5 Main Oscillator Specifications
          1. Table 5-12 Main Oscillator Input Characteristics
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
          1. Table 5-14 System Clock Characteristics With ADC Operation
        7. 5.15.4.7 System Clock Characteristics With USB Operation
          1. Table 5-15 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
        1. Table 5-16 Wake From Sleep Characteristics
        2. Table 5-17 Wake From Deep Sleep Characteristics
      6. 5.15.6  Hibernation Module
        1. Table 5-18 Hibernation Module Battery Characteristics
        2. Table 5-19 Hibernation Module Characteristics
        3. Table 5-20 Hibernation Module Tamper I/O Characteristics
      7. 5.15.7  Flash Memory
        1. Table 5-21 Flash Memory Characteristics
      8. 5.15.8  EEPROM
        1. Table 5-22 EEPROM Characteristics
      9. 5.15.9  Input/Output Pin Characteristics
        1. Table 5-23 Fast GPIO Module Characteristics
        2. Table 5-24 Slow GPIO Module Characteristics
        3. 5.15.9.1    Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
            1. Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin
          2. 5.15.9.1.2 Nonpower I/O Pins
            1. Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics
      10. 5.15.10 External Peripheral Interface (EPI)
        1. Table 5-28 EPI SDRAM Characteristics
        2. Table 5-29 EPI SDRAM Interface Characteristics
        3. Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
        4. Table 5-31 EPI General-Purpose Interface Characteristics
        5. Table 5-32 EPI PSRAM Interface Characteristics
      11. 5.15.11 Analog-to-Digital Converter (ADC)
        1. Table 5-33 Electrical Characteristics for ADC at 1 Msps
        2. Table 5-34 Electrical Characteristics for ADC at 2 Msps
      12. 5.15.12 Synchronous Serial Interface (SSI)
        1. Table 5-35 SSI Characteristics
        2. Table 5-36 Bi- and Quad-SSI Characteristics
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
        1. Table 5-37 I2C Characteristics
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
          1. Table 5-38 Ethernet PHY DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
          1. Table 5-39 MOSC 25-MHz Crystal Specification
          2. Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification
          3. Table 5-41 EN0RREF_CLK 50-MHz Oscillator Specification
        3. 5.15.14.3 AC Characteristics
          1. Table 5-42 Ethernet Controller Enable and Software Reset Timing
          2. Table 5-43 MII Serial Management Timing
          3. Table 5-44 100-Mbps MII Transmit Timing
          4. Table 5-45 100-Mbps MII Receive Timing
          5. Table 5-46 100Base-TX Transmit Timing
          6. Table 5-47 10-Mbps MII Transmit Timing
          7. Table 5-48 10-Mbps MII Receive Timing
          8. Table 5-49 10Base-T Normal Link Pulse Timing
          9. Table 5-50 Auto-Negotiation Fast Link Pulse (FLP) Timing
          10. Table 5-51 100Base-TX Signal Detect Timing
          11. Table 5-52 RMII Transmit Timing
          12. Table 5-53 RMII Receive Timing
      15. 5.15.15 Universal Serial Bus (USB) Controller
        1. Table 5-54 ULPI Interface Timing
      16. 5.15.16 LCD Controller
        1. Table 5-55 LCD Controller Load Capacitance Limits
        2. 5.15.16.1   LCD Interface Display Driver (LIDD Mode)
          1. Table 5-56 LCD Switching Characteristics
          2. Table 5-57 Timing Requirements for LCDDATA in LIDD Mode
          3. 5.15.16.1.1 Hitachi Mode
          4. 5.15.16.1.2 Motorola 6800 Mode
          5. 5.15.16.1.3 Intel 8080 Mode
        3. 5.15.16.2   LCD Raster Mode
          1. Table 5-58 Switching Characteristics for LCD Raster Mode
      17. 5.15.17 Analog Comparator
        1. Table 5-59 Analog Comparator Characteristics
        2. Table 5-60 Analog Comparator Characteristics
        3. Table 5-61 Analog Comparator Voltage Reference Characteristics
        4. Table 5-62 Analog Comparator Voltage Reference Characteristics
      18. 5.15.18 Pulse-Width Modulator (PWM)
        1. Table 5-63 PWM Timing Characteristics
      19. 5.15.19 Emulation and Debug
        1. Table 5-64 JTAG Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 1-Wire Master Module
        6. 6.5.6.6 Inter-Integrated Circuit (I2C)
        7. 6.5.6.7 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  LCD Controller
      9. 6.5.9  Advanced Motion Control
        1. 6.5.9.1 Pulse Width Modulation (PWM)
        2. 6.5.9.2 Quadrature Encoder With Index (QEI) Module
      10. 6.5.10 Analog
        1. 6.5.10.1 ADC
        2. 6.5.10.2 Analog Comparators
      11. 6.5.11 JTAG and Arm Serial Wire Debug
      12. 6.5.12 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和后续步骤
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 Community Resources
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 出口管制提示
    9. 8.9 术语表
  9. 9机械、封装和可订购信息

4.3 Signal Descriptions

Table 4-3 describes the signals. The signals are sorted by function.

Table 4-3 Signal Descriptions

FUNCTIONSIGNAL NAMEPIN NUMBERPIN TYPEDESCRIPTION
1-Wire OWALT K15 I/O 1-Wire optional second signal to be used as output
B12
OWIRE G2 I/O 1-Wire single bus pin. This signal is input only if 1-Wire alternate output is enabled
K17
V12
U14
D8
A8
ADC AIN0 I Analog-to-digital converter input 0
AIN1 Analog-to-digital converter input 1
AIN2 Analog-to-digital converter input 2
AIN3 Analog-to-digital converter input 3
AIN4 Analog-to-digital converter input 4
AIN5 Analog-to-digital converter input 5
AIN6 Analog-to-digital converter input 6
AIN7 Analog-to-digital converter input 7
AIN8 Analog-to-digital converter input 8
AIN9 Analog-to-digital converter input 9
AIN10 Analog-to-digital converter input 10
AIN11 Analog-to-digital converter input 11
AIN12 Analog-to-digital converter input 12
AIN13 Analog-to-digital converter input 13
AIN14 Analog-to-digital converter input 14
AIN15 Analog-to-digital converter input 15
AIN16 Analog-to-digital converter input 16
AIN17 Analog-to-digital converter input 17
AIN18 Analog-to-digital converter input 18
AIN19 Analog-to-digital converter input 19
AIN20 Analog-to-digital converter input 20
AIN21 Analog-to-digital converter input 21
AIN22 Analog-to-digital converter input 22
AIN23 Analog-to-digital converter input 23
VREFA+ – A reference voltage used to specify the voltage at which the ADC converts to a maximum value. This pin is used in conjunction with VREFA-, which specifies the minimum value. The voltage that is applied to VREFA+ is the voltage with which an AINn signal is converted to 4095. The VREFA+ voltage is limited to the range specified in Table 5-33.
VREFA- A reference voltage used to specify the input voltage at which the ADC converts to a minimum value. This pin is used in conjunction with VREFA+, which specifies the maximum value. In other words, the voltage that is applied to VREFA- is the voltage with which an AINn signal is converted to 0, while the voltage that is applied to VREFA+ is the voltage with which an AINn signal is converted to 4095. The VREFA- voltage is limited to the range specified in Table 5-33.
Analog Comparators C0+ L2 I Analog comparator 0 positive input
C0- K3 I Analog comparator 0 negative input
C0o C2 O Analog comparator 0 output
G18
C1+ M1 I Analog comparator 1 positive input
C1- M2 I Analog comparator 1 negative input
C1o C1 O Analog comparator 1 output
J18
C2+ D6 I Analog comparator 2 positive input
C2- D7 I Analog comparator 2 negative input
C2o D2 O Analog comparator 2 output
Controller Area Network CAN0Rx V3 I CAN module 0 receive
W10
CAN0Tx W3 O CAN module 0 transmit
V10
CAN1Rx A16 I CAN module 1 receive
E18
CAN1Tx B16 O CAN module 1 transmit
F17
Core TRCLK T7 O Trace clock
TRD0 W6 Trace data 0
TRD1 V6 Trace data 1
TRD2 U6 Trace data 2
TRD3 V7 Trace data 3
Ethernet EN0COL N18 I Ethernet 0 collision detect
EN0CRS N19 I Ethernet 0 carrier sense
EN0INTRN U19 I Ethernet 0 interrupt from the Ethernet PHY
D6
EN0LED0 U6 O Ethernet 0 LED 0
U19
EN0LED1 V7 O Ethernet 0 LED 1
V16
EN0LED2 V6 O Ethernet 0 LED 2
V17
EN0MDC A17 O Ethernet 0 management data clock
W6
EN0MDIO B17 I/O Ethernet 0 management data input/output signal
T7
EN0PPS N15 O Ethernet 0 pulse-per-second (PPS) output
T2
C8
EN0RREF_CLK M18 I/O Ethernet 0 reference clock
EN0RXCK V5 I Ethernet 0 receive clock
EN0RXD0 W12 I Ethernet 0 receive data 0
W10
EN0RXD1 U15 I Ethernet 0 receive data 1
V10
EN0RXD2 V17 I Ethernet 0 receive data 2
EN0RXD3 U19 I Ethernet 0 receive data 3
EN0RXDV U14 I Ethernet 0 receive data valid
R13
EN0RXER V12 I Ethernet 0 receive error
U10
EN0RXIN V13 I/O Ethernet PHY negative receive differential input
EN0RXIP W13 I/O Ethernet PHY positive receive differential input
EN0TXCK V11 I/O Ethernet 0 transmit clock
EN0TXD0 K17 O Ethernet 0 transmit data 0
V9
EN0TXD1 K15 O Ethernet 0 transmit data 1
T13
EN0TXD2 V16 O Ethernet 0 transmit data 2
EN0TXD3 W16 O Ethernet 0 transmit data 3
EN0TXEN M16 O Ethernet 0 transmit enable
R10
EN0TXER T12 O Ethernet 0 transmit error
EN0TXON V14 I/O Ethernet PHY negative transmit differential output
EN0TXOP V15 I/O Ethernet PHY positive transmit differential output
RBIAS W15 O 4.87-kΩ resistor (1% precision) for Ethernet PHY
External Peripheral Interface EPI0S0 P4 I/O EPI module 0 signal 0
J1
EPI0S1 R2 I/O EPI module 0 signal 1
J2
EPI0S2 R1 I/O EPI module 0 signal 2
K1
EPI0S3 T1 I/O EPI module 0 signal 3
K2
EPI0S4 K3 I/O EPI module 0 signal 4
EPI0S5 L2 I/O EPI module 0 signal 5
EPI0S6 M1 I/O EPI module 0 signal 6
EPI0S7 M2 I/O EPI module 0 signal 7
EPI0S8 V5 I/O EPI module 0 signal 8
EPI0S9 R7 I/O EPI module 0 signal 9
EPI0S10 T14 I/O EPI module 0 signal 10
EPI0S11 N15 I/O EPI module 0 signal 11
EPI0S12 L19 I/O EPI module 0 signal 12
EPI0S13 L18 I/O EPI module 0 signal 13
EPI0S14 K19 I/O EPI module 0 signal 14
EPI0S15 K18 I/O EPI module 0 signal 15
EPI0S16 G16 I/O EPI module 0 signal 16
EPI0S17 H19 I/O EPI module 0 signal 17
EPI0S18 G18 I/O EPI module 0 signal 18
EPI0S19 J18 I/O EPI module 0 signal 19
EPI0S20 E3 I/O EPI module 0 signal 20
EPI0S21 E2 I/O EPI module 0 signal 21
EPI0S22 H4 I/O EPI module 0 signal 22
EPI0S23 M4 I/O EPI module 0 signal 23
EPI0S24 W16 I/O EPI module 0 signal 24
EPI0S25 V16 I/O EPI module 0 signal 25
EPI0S26 H18 I/O EPI module 0 signal 26
EPI0S27 A17 I/O EPI module 0 signal 27
EPI0S28 B17 I/O EPI module 0 signal 28
EPI0S29 A11 I/O EPI module 0 signal 29
B13
EPI0S30 B10 I/O EPI module 0 signal 30
C12
EPI0S31 V17 I/O EPI module 0 signal 31
EPI0S32 U19 I/O EPI module 0 signal 32
EPI0S33 G19 I/O EPI module 0 signal 33
EPI0S34 A10 I/O EPI module 0 signal 34
EPI0S35 B9 I/O EPI module 0 signal 35
General-Purpose Timers T0CCP0 V3 I/O 16- and 32-bit Timer 0 capture, compare, or PWM 0
C2
H18
P3
T0CCP1 W3 I/O 16- and 32-bit Timer 0 capture, compare, or PWM 1
C1
G19
P2
T1CCP0 T6 I/O 16- and 32-bit Timer 1 capture, compare, or PWM 0
D2
C18
W9
T1CCP1 U5 I/O 16- and 32-bit Timer 1 capture, compare, or PWM 1
D1
B18
R10
T2CCP0 V4 I/O 16- and 32-bit Timer 2 capture, compare, or PWM 0
K18
D12
T2CCP1 W4 I/O 16- and 32-bit Timer 2 capture, compare, or PWM 1
K19
D13
T3CCP0 V5 I/O 16- and 32-bit Timer 3 capture, compare, or PWM 0
A4
L18
B14
T3CCP1 R7 I/O 16- and 32-bit Timer 3 capture, compare, or PWM 1
B4
L19
A14
T4CCP0 A16 I/O 16- and 32-bit Timer 4 capture, compare, or PWM 0
B3
M18
V9
T4CCP1 B16 I/O 16- and 32-bit Timer 4 capture, compare, or PWM 1
B2
G15
T13
General-Purpose Timers (continued) T5CCP0 A17 I/O 16- and 32-bit Timer 5 capture, compare, or PWM 0
N19
U10
T5CCP1 B17 I/O 16- and 32-bit Timer 5 capture, compare, or PWM 1
N18
R13
T6CCP0 F2 I/O 16- and 32-bit Timer 6 capture, compare, or PWM 0
D6
E3
W10
T6CCP1 F1 I/O 16- and 32-bit Timer 6 capture, compare, or PWM 1
D7
E2
V10
T7CCP0 M2 I/O 16- and 32-bit Timer 7 capture, compare, or PWM 0
H4
E18
T7CCP1 M1 I/O 16- and 32-bit Timer 7 capture, compare, or PWM 1
M4
F17
GPIO, Port A PA0 V3 I/O GPIO port A bit 0
PA1 W3 I/O GPIO port A bit 1
PA2 T6 I/O GPIO port A bit 2
PA3 U5 I/O GPIO port A bit 3
PA4 V4 I/O GPIO port A bit 4
PA5 W4 I/O GPIO port A bit 5
PA6 V5 I/O GPIO port A bit 6
PA7 R7 I/O GPIO port A bit 7
GPIO, Port B PB0 A16 I/O GPIO port B bit 0
PB1 B16 I/O GPIO port B bit 1
PB2 A17 I/O GPIO port B bit 2
PB3 B17 I/O GPIO port B bit 3
PB4 C6 I/O GPIO port B bit 4
PB5 B6 I/O GPIO port B bit 5
PB6 F2 I/O GPIO port B bit 6
PB7 F1 I/O GPIO port B bit 7
GPIO, Port C PC0 B15 I/O GPIO port C bit 0
PC1 C15 I/O GPIO port C bit 1
PC2 D14 I/O GPIO port C bit 2
PC3 C14 I/O GPIO port C bit 3
PC4 M2 I/O GPIO port C bit 4
PC5 M1 I/O GPIO port C bit 5
PC6 L2 I/O GPIO port C bit 6
PC7 K3 I/O GPIO port C bit 7
GPIO, Port D PD0 C2 I/O GPIO port D bit 0
PD1 C1 I/O GPIO port D bit 1
PD2 D2 I/O GPIO port D bit 2
PD3 D1 I/O GPIO port D bit 3
PD4 A4 I/O GPIO port D bit 4
PD5 B4 I/O GPIO port D bit 5
PD6 B3 I/O GPIO port D bit 6
PD7 B2 I/O GPIO port D bit 7
GPIO, Port E PE0 H3 I/O GPIO port E bit 0
PE1 H2 I/O GPIO port E bit 1
PE2 G1 I/O GPIO port E bit 2
PE3 G2 I/O GPIO port E bit 3
PE4 A5 I/O GPIO port E bit 4
PE5 B5 I/O GPIO port E bit 5
PE6 A7 I/O GPIO port E bit 6
PE7 B7 I/O GPIO port E bit 7
GPIO, Port F PF0 U6 I/O GPIO port F bit 0
PF1 V6 I/O GPIO port F bit 1
PF2 W6 I/O GPIO port F bit 2
PF3 T7 I/O GPIO port F bit 3
PF4 V7 I/O GPIO port F bit 4
PF5 W7 I/O GPIO port F bit 5
PF6 T8 I/O GPIO port F bit 6
PF7 U8 I/O GPIO port F bit 7
GPIO, Port G PG0 N15 I/O GPIO port G bit 0
PG1 T14 I/O GPIO port G bit 1
PG2 V11 I/O GPIO port G bit 2
PG3 M16 I/O GPIO port G bit 3
PG4 K17 I/O GPIO port G bit 4
PG5 K15 I/O GPIO port G bit 5
PG6 V12 I/O GPIO port G bit 6
PG7 U14 I/O GPIO port G bit 7
GPIO, Port H PH0 P4 I/O GPIO port H bit 0
PH1 R2 I/O GPIO port H bit 1
PH2 R1 I/O GPIO port H bit 2
PH3 T1 I/O GPIO port H bit 3
PH4 R3 I/O GPIO port H bit 4
PH5 T2 I/O GPIO port H bit 5
PH6 U2 I/O GPIO port H bit 6
PH7 V2 I/O GPIO port H bit 7
GPIO, Port J PJ0 C8 I/O GPIO port J bit 0
PJ1 E7 I/O GPIO port J bit 1
PJ2 H17 I/O GPIO port J bit 2
PJ3 F16 I/O GPIO port J bit 3
PJ4 F18 I/O GPIO port J bit 4
PJ5 E17 I/O GPIO port J bit 5
PJ6 N1 I/O GPIO port J bit 6
PJ7 K5 I/O GPIO port J bit 7
GPIO, Port K PK0 J1 I/O GPIO port K bit 0
PK1 J2 I/O GPIO port K bit 1
PK2 K1 I/O GPIO port K bit 2
PK3 K2 I/O GPIO port K bit 3
PK4 U19 I/O GPIO port K bit 4
PK5 V17 I/O GPIO port K bit 5
PK6 V16 I/O GPIO port K bit 6
PK7 W16 I/O GPIO port K bit 7
GPIO, Port L PL0 G16 I/O GPIO port L bit 0
PL1 H19 I/O GPIO port L bit 1
PL2 G18 I/O GPIO port L bit 2
PL3 J18 I/O GPIO port L bit 3
PL4 H18 I/O GPIO port L bit 4
PL5 G19 I/O GPIO port L bit 5
PL6 C18 I/O GPIO port L bit 6
PL7 B18 I/O GPIO port L bit 7
GPIO, Port M PM0 K18 I/O GPIO port M bit 0
PM1 K19 I/O GPIO port M bit 1
PM2 L18 I/O GPIO port M bit 2
PM3 L19 I/O GPIO port M bit 3
PM4 M18 I/O GPIO port M bit 4
PM5 G15 I/O GPIO port M bit 5
PM6 N19 I/O GPIO port M bit 6
PM7 N18 I/O GPIO port M bit 7
GPIO, Port N PN0 C10 I/O GPIO port N bit 0
PN1 B11 I/O GPIO port N bit 1
PN2 A11 I/O GPIO port N bit 2
PN3 B10 I/O GPIO port N bit 3
PN4 A10 I/O GPIO port N bit 4
PN5 B9 I/O GPIO port N bit 5
PN6 T12 I/O GPIO port N bit 6
PN7 U12 I/O GPIO port N bit 7
GPIO, Port P PP0 D6 I/O GPIO port P bit 0
PP1 D7 I/O GPIO port P bit 1
PP2 B13 I/O GPIO port P bit 2
PP3 C12 I/O GPIO port P bit 3
PP4 D8 I/O GPIO port P bit 4
PP5 B12 I/O GPIO port P bit 5
PP6 B8 I/O GPIO port P bit 6
PP7 A8 I/O GPIO port P bit 7
GPIO, Port Q PQ0 E3 I/O GPIO port Q bit 0
PQ1 E2 I/O GPIO port Q bit 1
PQ2 H4 I/O GPIO port Q bit 2
PQ3 M4 I/O GPIO port Q bit 3
PQ4 A13 I/O GPIO port Q bit 4
PQ5 W12 I/O GPIO port Q bit 5
PQ6 U15 I/O GPIO port Q bit 6
PQ7 M3 I/O GPIO port Q bit 7
GPIO, Port R PR0 N5 I/O GPIO port R bit 0
PR1 N4 I/O GPIO port R bit 1
PR2 N2 I/O GPIO port R bit 2
PR3 V8 I/O GPIO port R bit 3
PR4 P3 I/O GPIO port R bit 4
PR5 P2 I/O GPIO port R bit 5
PR6 W9 I/O GPIO port R bit 6
PR7 R10 I/O GPIO port R bit 7
GPIO, Port S PS0 D12 I/O GPIO port S bit 0
PS1 D13 I/O GPIO port S bit 1
PS2 B14 I/O GPIO port S bit 2
PS3 A14 I/O GPIO port S bit 3
PS4 V9 I/O GPIO port S bit 4
PS5 T13 I/O GPIO port S bit 5
PS6 U10 I/O GPIO port S bit 6
PS7 R13 I/O GPIO port S bit 7
GPIO, Port T PT0 W10 I/O GPIO port T bit 0
PT1 V10 I/O GPIO port T bit 1
PT2 E18 I/O GPIO port T bit 2
PT3 F17 I/O GPIO port T bit 3
Hibernate GNDX R18 – GND for the Hibernation oscillator. When using a crystal clock source, connect this pin to digital ground along with the crystal load capacitors. When using an external oscillator, connect this pin to digital ground.
HIB M17 O An output that indicates the processor is in hibernate mode.
RTCCLK M1 O Buffered version of the 32.768-kHz clock of the Hibernation module. This signal is not output when the part is in hibernate mode and before being configured after power-on reset.
W16
C12
TMPR0 N18 I/O Tamper signal 0
TMPR1 N19 I/O Tamper signal 1
TMPR2 G15 I/O Tamper signal 2
TMPR3 M18 I/O Tamper signal 3
VBAT P19 – Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup and Hibernation module power-source supply.
WAKE U18 I An external input that brings the processor out of hibernate mode when asserted
XOSC0 T18 I Hibernation module oscillator crystal input or an external clock reference input. This is either a crystal or a 32.768-kHz oscillator for the RTC of the Hibernation module.
XOSC1 T19 O Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source.
I2C I2C0SCL A17 I/O I2C module 0 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
I2C0SDA B17 I/O I2C module 0 data
I2C1SCL N15 I/O I2C module 1 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
N5
I2C1SDA T14 I/O I2C module 1 data
N4
I2C2SCL V11 I/O I2C module 2 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
H19
B9
B12
N2
I2C2SDA M16 I/O I2C module 2 data
G16
A10
B8
V8
I2C3SCL K17 I/O I2C module 3 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
U19
P3
I2C3SDA K15 I/O I2C module 3 data
V17
P2
I2C4SCL V12 I/O I2C module 4 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
V16
W9
I2C4SDA U14 I/O I2C module 4 data
W16
R10
I2C5SCL A16 I/O I2C module 5 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
C6
I2C5SDA B16 I/O I2C module 5 data
B6
I2C6SCL V5 I/O I2C module 6 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
F2
I2C6SDA R7 I/O I2C module 6 data
F1
I2C7SCL V4 I/O I2C module 7 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
C2
I2C7SDA W4 I/O I2C module 7 data
C1
I2C8SCL T6 I/O I2C module 8 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
D2
I2C8SDA U5 I/O I2C module 8 data
D1
I2C (continued) I2C9SCL V3 I/O I2C module 9 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain.
A7
I2C9SDA W3 I/O I2C module 9 data
B7
JTAG, SWD, SWO TCLK/SWCLK B15 I JTAG and SWD clock
TDI D14 I JTAG TDI
TDO/SWO C14 O JTAG TDO and SWO
TMS/SWDIO C15 I JTAG TMS and SWDIO
LCD LCDAC N1 O LCD AC bias or latch enable in raster mode. Primary chip select (CS0) or primary enable (E0) in LIDD MPU/Hitachi mode.
LCDCP N5 O LCD pixel clock in raster mode. Read strobe or read/write strobe in LIDD mode.
LCDDATA00 P3 I/O LCD data pin 0 input/output
LCDDATA01 P2 I/O LCD data pin 1 input/output
LCDDATA02 U8 I/O LCD data pin 2 input/output
LCDDATA03 V8 I/O LCD data pin 3 input/output
LCDDATA04 W9 I/O LCD data pin 4 input/output
LCDDATA05 R10 I/O LCD data pin 5 input/output
LCDDATA06 V9 I/O LCD data pin 6 input/output
LCDDATA07 T13 I/O LCD data pin 7 input/output
LCDDATA08 U10 I/O LCD data pin 8 input/output
LCDDATA09 R13 I/O LCD data pin 9 input/output
LCDDATA10 W10 I/O LCD data pin 10 input/output
LCDDATA11 V10 I/O LCD data pin 11 input/output
LCDDATA12 U12 I/O LCD data pin 12 input/output
LCDDATA13 T12 I/O LCD data pin 13 input/output
LCDDATA14 H17 I/O LCD data pin 14 input/output
LCDDATA15 F16 I/O LCD data pin 15 input/output
LCDDATA16 F18 O LCD data pin 16 output
LCDDATA17 E17 O LCD data pin 17 output
LCDDATA18 E18 O LCD data pin 18 output
LCDDATA19 F17 O LCD data pin 19 output
LCDDATA20 D12 O LCD data pin 20 output
LCDDATA21 D13 O LCD data pin 21 output
LCDDATA22 B14 O LCD data pin 22 output
LCDDATA23 A14 O LCD data pin 23 output
LCDFP N4 O LCD frame clock or VSYNC in raster mode. Address latch enable in LIDD mode.
LCDLP N2 O LCD line clock or HSYNC in raster mode. Write strobe or direction bit in LIDD mode.
LCDMCLK T8 O LCD memory clock, secondary chip select (CS1), or secondary enable (E1) in LIDD synchronous or asynchronous MPU or Hitachi mode
PWM M0FAULT0 V7 I Motion control module 0 PWM fault 0
D12
M0FAULT1 V16 Motion control module 0 PWM fault 1
D13
M0FAULT2 W16 Motion control module 0 PWM fault 2
B14
M0FAULT3 G16 Motion control module 0 PWM fault 3
A14
M0PWM0 U6 O Motion control module 0 PWM 0. This signal is controlled by module 0 PWM generator 0.
N5
M0PWM1 V6 Motion control module 0 PWM 1. This signal is controlled by module 0 PWM generator 0.
N4
M0PWM2 W6 Motion control module 0 PWM 2. This signal is controlled by module 0 PWM generator 1.
N2
M0PWM3 T7 Motion control module 0 PWM 3. This signal is controlled by module 0 PWM generator 1.
V8
M0PWM4 N15 Motion control module 0 PWM 4. This signal is controlled by module 0 PWM generator 2.
P3
M0PWM5 T14 Motion control module 0 PWM 5. This signal is controlled by module 0 PWM generator 2.
P2
M0PWM6 U19 Motion control module 0 PWM 6. This signal is controlled by module 0 PWM generator 3.
W9
M0PWM7 V17 Motion control module 0 PWM 7. This signal is controlled by module 0 PWM generator 3.
R10
Power GND F10 – Ground reference for logic and I/O pins
H10
H11
H12
J11
J12
K6
K9
P16
K10
R17
K13
K14
L8
L9
M8
M9
M10
N10
A1
A2
B1
V1
W1
W2
A18
A19
B19
Power (continued) GNDA G4 – The ground reference for the analog circuits (ADC, Analog Comparators, and so on). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions.
VDD G10 – Positive supply for I/O and some logic
H9
J8
J9
J10
K7
K8
K11
N16
P17
K12
L10
L11
L12
M11
M12
P10
VDDA F3 – The positive supply for the analog circuits (for example, ADC and analog comparators). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in Section 5.4, regardless of system implementation.
VDDC H16 – Positive supply for most of the logic function, including the processor core and most peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO. The VDDC pins should only be connected to each other and an external capacitor as specified in Section 5.12.
E10
QEI IDX0 J18 I QEI module 0 index
U10
PhA0 H19 I QEI module 0 phase A
V9
PhB0 G18 I QEI module 0 phase B
T13
SSI SSI0Clk T6 I/O SSI module 0 clock
SSI0Fss U5 SSI module 0 frame signal
SSI0XDAT0 V4 SSI Module 0 bidirectional data pin 0 (SSI0TX in Legacy SSI Mode)
SSI0XDAT1 W4 SSI Module 0 bidirectional data pin 1 (SSI0RX in Legacy SSI Mode)
SSI0XDAT2 V5 SSI Module 0 bidirectional data pin 2
SSI0XDAT3 R7 SSI Module 0 bidirectional data pin 3
SSI1Clk B6 SSI module 1 clock
SSI1Fss C6 SSI module 1 frame signal
SSI1XDAT0 A5 SSI Module 1 bidirectional data pin 0 (SSI1TX in Legacy SSI Mode)
SSI1XDAT1 B5 SSI Module 1 bidirectional data pin 1 (SSI1RX in Legacy SSI Mode)
SSI1XDAT2 A4 SSI Module 1 bidirectional data pin 2
SSI1XDAT3 B4 SSI Module 1 bidirectional data pin 3
SSI2Clk D1 SSI module 2 clock
U14
SSI2Fss D2 SSI module 2 frame signal
V12
SSI2XDAT0 C1 SSI Module 2 bidirectional data pin 0 (SSI2TX in Legacy SSI Mode)
K15
SSI2XDAT1 C2 SSI Module 2 bidirectional data pin 1 (SSI2RX in Legacy SSI Mode)
K17
SSI2XDAT2 B2 SSI Module 2 bidirectional data pin 2
M16
SSI2XDAT3 B3 SSI Module 2 bidirectional data pin 3
V11
SSI3Clk T7 SSI module 3 clock
E3
SSI3Fss W6 SSI module 3 frame signal
E2
SSI3XDAT0 V6 SSI Module 3 bidirectional data pin 0 (SSI3TX in Legacy SSI Mode)
H4
SSI3XDAT1 U6 SSI Module 3 bidirectional data pin 1 (SSI3RX in Legacy SSI Mode)
M4
SSI3XDAT2 V7 SSI Module 3 bidirectional data pin 2
D6
SSI3XDAT3 W7 SSI Module 3 bidirectional data pin 3
D7
System Control and Clocks DIVSCLK A13 O An optionally divided reference clock output based on a selected clock source. This signal is not synchronized to the system clock.
GNDX2 D18 – GND for the MOSC. When using a crystal clock source, connect this pin to digital ground along with the crystal load capacitors. When using an external oscillator, connect this pin to digital ground.
NMI B2 I Nonmaskable interrupt
B7
OSC0 E19 Main oscillator crystal input or an external clock reference input
OSC1 D19 O Main oscillator crystal output. Leave unconnected when using a single-ended clock source.
RST P18 I System reset input
UART U0CTS C6 I UART module 0 clear to send modem flow control input signal
A7
K17
R2
M18
U0DCD R1 I UART module 0 data carrier detect modem status input signal
G15
C12
U0DSR T1 I UART module 0 data set ready modem output control line
N19
D8
U0DTR R3 O UART module 0 data terminal ready modem status input signal
B13
U0RI T2 I UART module 0 ring indicator modem status input signal
W16
N18
U0RTS B6 O UART module 0 request to send modem flow control output signal
B7
K15
P4
U0Rx V3 I UART module 0 receive
U0Tx W3 O UART module 0 transmit
U1CTS B11 I UART module 1 clear to send modem flow control input signal
C12
U1DCD G1 I UART module 1 data carrier detect modem status input signal
A11
B8
U1DSR H2 I UART module 1 data set ready modem output control line
B10
B14
U1DTR G2 O UART module 1 data terminal ready modem status input signal
A10
U15
U1RI A5 I UART module 1 ring indicator modem status input signal
B9
M3
U1RTS H3 O UART module 1 request to send modem flow control output line
C10
U12
U1Rx A16 I UART module 1 receive
A13
P2
U1Tx B16 O UART module 1 transmit
W12
W9
UART (continued) U2CTS B2 I UART module 2 clear to send modem flow control input signal
F16
B10
U2RTS B3 O UART module 2 request to send modem flow control output line
H17
A11
U2Rx V5 I UART module 2 receive
A4
U2Tx R7 O UART module 2 transmit
B4
U3CTS E17 I UART module 3 clear to send modem flow control input signal
B9
B12
U3RTS F18 O UART module 3 request to send modem flow control output line
A10
D8
U3Rx V4 I UART module 3 receive
C8
U3Tx W4 O UART module 3 transmit
E7
U4CTS K5 I UART module 4 clear to send modem flow control input signal
K2
U12
U4RTS N1 O UART module 4 request to send modem flow control output line
K1
T12
U4Rx T6 I UART module 4 receive
J1
N4
U4Tx U5 O UART module 4 transmit
J2
N5
U5Rx L2 I UART module 5 receive
U2
U5Tx K3 O UART module 5 transmit
V2
U6Rx D6 I UART module 6 receive
U6Tx D7 O UART module 6 transmit
U7Rx M2 I UART module 7 receive
U2
U7Tx M1 O UART module 7 transmit
V2
USB USB0CLK B17 O 60-MHz clock to the external PHY
USB0D0 G16 I/O USB data 0
USB0D1 H19 USB data 1
USB0D2 G18 USB data 2
USB0D3 J18 USB data 3
USB0D4 H18 USB data 4
USB0D5 G19 USB data 5
USB0D6 B12 USB data 6
USB0D7 D8 USB data 7
USB0DIR C12 O Indicates that the external PHY is able to accept data from the USB controller
USB0DM B18 I/O Bidirectional differential data pin (D– per USB specification) for USB0
USB0DP C18 Bidirectional differential data pin (D+ per USB specification) for USB0
USB0EPEN V5 O Optionally used in host mode to control an external power source to supply power to the USB bus
R7
B3
USB0ID A16 I This signal senses the state of the USB ID signal. The USB PHY enables an integrated pullup, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side).
USB0NXT B13 O Asserted by the external PHY to throttle all data types
USB0PFLT R7 I Optionally used in host mode by an external power source to indicate an error state by that power source
B2
USB0STP A17 O Asserted by the USB controller to signal the end of a USB transmit packet or register write operation
USB0VBUS B16 I/O This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing.