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  • UCC53x0 单通道隔离式栅极驱动器

    • ZHCSGC2I June   2017  – March 2024 UCC5310 , UCC5320 , UCC5350 , UCC5390

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  • UCC53x0 单通道隔离式栅极驱动器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6. 12.6 Trademarks
    7. 12.7 静电放电警告
    8. 12.8 术语表
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information
  16. 重要声明
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Data Sheet

UCC53x0 单通道隔离式栅极驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

下载最新的英语版本

1 特性

  • 特性选项
    • 分离输出 (UCC53x0S)
    • 以 GND2 为基准的 UVLO (UCC53x0E)
    • 米勒钳位选项 (UCC53x0M)
  • 8 引脚 D（4mm 爬电）和
    DWV（8.5mm 爬电）封装
  • 60ns（典型值）传播延迟
  • 100kV/μs 最小 CMTI
  • 隔离栅寿命 > 40 年
  • 3V 至 15V 输入电源电压
  • 驱动器电源电压高达 33V
    • 8V 和 12V UVLO 选项
  • 输入引脚具有负 5V 电压处理能力
  • 安全相关认证：
    • 符合 DIN V VDE V 0884-11:2017-01 和 DIN EN 61010-1 标准的 7000VPK 隔离 DWV（计划）和 4242VPK 隔离 D
    • 符合 UL 1577 标准且长达 1 分钟的 5000VRMS DWV 和 3000VRMS D
      隔离等级
    • 符合 GB4943.1-2011
      D 和 DWV 标准的 CQC 认证（计划）
  • CMOS 输入
  • 工作温度：-40°C 至 +125°C

2 应用

  • 电机驱动器
  • 高压直流到直流转换器
  • UPS 和 PSU
  • HEV 和 EV 电源模块
  • 光伏逆变器

3 说明

UCC53x0 是单通道隔离式栅极驱动器系列，旨在驱动 MOSFET、IGBT、SiC MOSFET 和 GaN FET (UCC5350SBD)。UCC53x0S 提供分离输出，可分别控制上升和下降时间。UCC53x0M 将晶体管的栅极连接到内部钳位，以防止米勒电流造成假接通。UCC53x0E 的 UVLO2 以 GND2 为基准，以获取真实的 UVLO 读数。

UCC53x0 采用 4mm SOIC-8 (D) 或 8.5mm SOIC-8 (DWV) 封装，可分别支持高达 3kVRMS 和 5kVRMS 的隔离电压。凭借这些各种不同的选项，UCC53x0 系列成为电机驱动器和工业电源的理想之选。

与光耦合器相比，UCC53x0 系列的器件间偏移更低，传播延迟更小，工作温度更高，并且 CMTI 更高。

器件信息
可订购器件型号(1)(2) 最低拉电流和灌电流 说明
UCC5310MC 2.4A 和 1.1A 米勒钳位
UCC5320SC 2.4A 和 2.2A 分离输出
UCC5320EC 2.4A 和 2.2A UVLO 以 IGBT 发射极为基准
UCC5350MC 5A 和 5A 米勒钳位
UCC5350SB 5A 和 5A 具有 8V UVLO 的分离输出
UCC5390SC 10A 和 10A 分离输出
UCC5390EC 10A 和 10A UVLO 以 IGBT 发射极为基准
(1) 有关所有可选封装，请参阅节 14。
(2) 有关器件的详细比较，请参阅节 4。
GUID-8DC79883-B940-4FD8-BEEC-87ACA8C26DFF-low.gif功能框图（S、E 和 M 版本）

4 Device Comparison Table

DEVICE OPTION(1) PACKAGE MINIMUM SOURCE CURRENT MINIMUM SINK CURRENT PIN CONFIGURATION UVLO ISOLATION RATING
UCC5310MC D 2.4 A 1.1 A Miller clamp 12 V 3-kVRMS
DWV 5-kVRMS
UCC5320EC D 2.4 A 2.2 A UVLO with reference to GND2 12 V 3-kVRMS
UCC5320SC D 2.4 A 2.2 A Split output 12 V 3-kVRMS
DWV 5-kVRMS
UCC5350MC D 5 A 5 A Miller clamp 12 V 3-kVRMS
DWV 5-kVRMS
UCC5350SB D 5 A 5 A Split Output 8 V 3-kVRMS
UCC5390EC D 10 A 10 A UVLO with reference to GND2 12 V 3-kVRMS
DWV 5-kVRMS
UCC5390SC D 10 A 10 A Split output 12 V 3-kVRMS
(1) The S, E, and M suffixes are part of the orderable part number. See Section 14 for the full orderable part number.

5 Pin Configuration and Function

GUID-477F73E1-FBDB-4D66-A7DA-3069010B9316-low.svg Figure 5-1 UCC5320S, UCC5350SB, and UCC5390S 8-Pin SOICTop View
GUID-B7CD873A-1302-428A-B17B-2CDA1C00DE4F-low.svg Figure 5-2 UCC5310M and UCC5350M 8-Pin SOICTop View
GUID-B5522B11-F400-4BF0-A8E0-4E911D2FA007-low.svg Figure 5-3 UCC5320E and UCC5390E 8-Pin SOICTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
UCC53x0S UCC53x0M UCC53x0E
CLAMP — 7 — I Active Miller-clamp input found on the UCC53x0M used to prevent false turnon of the power switches.
GND1 4 4 4 G Input ground. All signals on the input side are referenced to this ground.
GND2 — — 7 G Gate-drive common pin. Connect this pin to the IGBT emitter. UVLO referenced to GND2 in the UCC53x0E.
IN+ 2 2 2 I Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS input threshold. This pin is pulled low internally if left open. Use Table 8-4 to understand the input and output logic of these devices.
IN– 3 3 3 I Inverting gate-drive voltage control input. The IN– pin has a CMOS input threshold. This pin is pulled high internally if left open. Use Table 8-4 to understand the input and output logic of these devices.
OUT — 6 6 O Gate-drive output for UCC53x0E and UCC53x0M versions.
OUTH 6 — — O Gate-drive pull-up output found on the UCC53x0S.
OUTL 7 — — O Gate-drive pull-down output found on the UCC53x0S.
VCC1 1 1 1 P Input supply voltage. Connect a locally decoupled capacitor to GND. Use a low-ESR or ESL capacitor located as close to the device as possible.
VCC2 5 5 5 P Positive output supply rail. Connect a locally decoupled capacitor to VEE2. Use a low-ESR or ESL capacitor located as close to the device as possible.
VEE2 8 8 8 P Negative output supply rail for E version, and GND for S and M versions. Connect a locally decoupled capacitor to GND2 for E version. Use a low-ESR or ESL capacitor located as close to the device as possible.
(1) P = Power, G = Ground, I = Input, O = Output

6 Specifications

 
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