SWRU359F September   2015  – December 2021 WL1801MOD , WL1805MOD , WL1831MOD , WL1835MOD

 

  1.   Trademarks
  2.   Warning
  3. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 TI Module Key Benefits
  4. 2Board Pin Assignment
    1. 2.1 Pin Descriptions
  5. 3Electrical Characteristics
  6. 4Approved Antenna Types and Maximum Gain Values
  7. 5On-Board Antenna Configuration
    1. 5.1 VSWR
    2. 5.2 Efficiency
    3. 5.3 Radio Pattern
    4. 5.4 ANT1
    5. 5.5 ANT2
  8. 6Circuit Design
    1. 6.1 Schematic
    2. 6.2 Bill of Materials (BOM)
  9. 7Layout Guidelines
    1. 7.1 Board Layout
  10. 8Revision History

7.1 Board Layout

Figure 7-1 shows the WL1835MODCOM8B 4-layer board. Table 7-1, Figure 7-2, Figure 7-3, Figure 7-4, Figure 7-5, and Figure 7-6 show instances of good layout practices.

GUID-CB3D00E7-41E6-4DE9-B4C8-2143D3498BAE-low.png Figure 7-1 Layer 1
GUID-0F6C9CF5-93FD-4B61-9CE2-F8283DDFE275-low.png Figure 7-2 Layer 2
GUID-BB74DE33-D6FA-4E2B-8BAE-A340CA5082A2-low.png Figure 7-3 Layer 3
GUID-47A813A8-DA73-48AB-B046-03C71F9B61D4-low.png Figure 7-4 Layer 4
Table 7-1 Module Layout Guidelines
Reference Guideline Description
1 The proximity of ground vias must be close to the pad.
2 Signal traces must not be run underneath the module on the layer where the module is mounted.
3 Have a complete ground pour in layer 2 for thermal dissipation.
4 Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.
5 Increase the ground pour in the first layer and have all of the traces from the first layer on the inner layers, if possible.
6 Signal traces can be run on a third layer under the solid ground layer, which is below the module mounting layer.
GUID-ECD16F2F-EF6F-41B8-9ABB-FEAE7B5C6436-low.png Figure 7-5 Module Layout Guidelines (Top Layer)
GUID-AC45376F-EFE3-44DA-BE1E-77DB11719B97-low.png Figure 7-6 Module Layout Guidelines (Bottom Layer)

Figure 7-7 shows the trace design for the PCB. A 50-Ω impedance match on the trace to the antenna should be used. Also, 50-Ω traces are recommended for the PCB layout.

GUID-BF928390-8C80-4B82-98A3-B30083040163-low.png Figure 7-7 Trace Design for the PCB Layout

Figure 7-8 shows layer 1 with the trace to the antenna over ground layer 2.

GUID-933A46CD-950A-460B-ABF8-D62C4503F1D2-low.png Figure 7-8 Layer 1 Combined With Layer 2

Table 7-2, Figure 7-9, and Figure 7-10 describe instances of good layout practices for the antenna and RF trace routing.

Table 7-2 Antenna and RF Trace Routing Layout Guidelines
Reference Guideline Description
1 The RF trace antenna feed must be as short as possible beyond the ground reference. At this point, the trace starts to radiate.
2 The RF trace bends must be gradual with an approximate maximum bend of 45 degrees with trace mitered. RF traces must not have sharp corners.
3 RF traces must have via stitching on the ground plane beside the RF trace on both sides
4 RF traces must have constant impedance (microstrip transmission line).
5 For best results, the RF trace ground layer must be the ground layer immediately below the RF trace. The ground layer must be solid.
6 There must be no traces or ground under the antenna section.
7 RF traces must be as short as possible. The antenna, RF traces, and modules must be on the edge of the PCB product. The proximity of the antenna to the enclosure and the enclosure material must also be considered.
GUID-676D15C0-052D-4958-A263-7D4813E06532-low.png Figure 7-9 Top Layer – Antenna and RF Trace Routing Layout Guidelines
GUID-9302BAE2-B8BC-4BE3-A886-EC2BDA167ACD-low.png Figure 7-10 Bottom Layer – Antenna and RF Trace Routing Layout Guidelines

Figure 7-11 describes the MIMO antenna spacing. The distance of ANT1 and ANT2 must be greater than half of wavelength (62.5 mm at 2.4 GHz).

GUID-3250D175-86FA-40F6-9718-F776EA7D2658-low.png Figure 7-11 MIMO Antenna Spacing

The supply routing guidelines are as follows:

  • For power supply routing, the power trace for VBAT must be at least 40-mil wide.
  • The 1.8-V trace must be at least 18-mil wide.
  • Make VBAT traces as wide as possible to ensure reduced inductance and trace resistance.
  • If possible, shield VBAT traces with ground above, below, and beside the traces.

The digital-signal routing guidelines are as follows:

  • Route SDIO signal traces (CLK, CMD, D0, D1, D2, and D3) in parallel to each other and as short as possible (less than 12 cm). In addition, each trace must be the same length. Ensure enough space between traces (greater than 1.5 times the trace width or ground) to ensure signal quality, especially for the SDIO_CLK trace. Remember to keep these traces away from the other digital or analog signal traces. TI recommends adding ground shielding around these buses.
  • Digital clock signals (SDIO clock, PCM clock, and so on) are a source of noise. Keep the traces of these signals as short as possible. Whenever possible, maintain a clearance around these signals.