SPRZ292S December   2008  – November 2020 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28022-Q1 , TMS320F280220 , TMS320F28023 , TMS320F28023-Q1 , TMS320F280230 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F280270 , TMS320F28027F , TMS320F28027F-Q1

 

  1.   TMS320F2802x, TMS320F2802xx MCUs Silicon Revisions B, A, 0
  2. 1Introduction
  3. 2Device and Development Support Tool Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
      2. 4.1.2 Flash: MAX "Program Time” and “Erase Time” in Revision O of the TMS320F2802x Microcontrollers Data Manual are only Applicable for Devices Manufactured After October 2020
    2. 4.2 Known Design Exceptions to Functional Specifications
      1.      Advisory to Silicon Variant / Revision Map
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
  6. 5Documentation Support
  7. 6Trademarks
  8. 7Revision History

Advisory

ADC: DC Specifications: Linearity Limitation

Revision(s) Affected

0, A, B

Details

The linearity degrades with increasing temperature in the upper half of the transfer function.

Workaround(s)

The impact from this limitation has been addressed in the revision A silicon. The following features have been added:

  1. ADC clock divider-by-2 enable bit. At 60 MHz, the effective sample rate will be
    2.3 MSPS. This offers a 30-MHz ADC and a 60-MHz system clock, and improves linearity.
  2. Existing pipeline mode with 4.6 MSPS at 60-MHz system clock will have improved linearity compared to revision 0 silicon.

Note:

For 60-MHz operation, there are periodic missing codes, and INL will be bounded by ±28 LSBs MAX/MIN.

For 30-MHz operation, see the TMS320F2802x Microcontrollers Data Manual and the TMS320F2802x0 Microcontrollers Data Manual.