SPRZ292S December   2008  – November 2020 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28022-Q1 , TMS320F280220 , TMS320F28023 , TMS320F28023-Q1 , TMS320F280230 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F280270 , TMS320F28027F , TMS320F28027F-Q1

 

  1.   TMS320F2802x, TMS320F2802xx MCUs Silicon Revisions B, A, 0
  2. 1Introduction
  3. 2Device and Development Support Tool Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
      2. 4.1.2 Flash: MAX "Program Time” and “Erase Time” in Revision O of the TMS320F2802x Microcontrollers Data Manual are only Applicable for Devices Manufactured After October 2020
    2. 4.2 Known Design Exceptions to Functional Specifications
      1.      Advisory to Silicon Variant / Revision Map
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
  6. 5Documentation Support
  7. 6Trademarks
  8. 7Revision History

Advisory

ADC: New ADC Control Bits Added to Revision A Silicon

Revision(s) Affected

A, B

Details

The following bits/features have been added to the ADC control registers in the revision A silicon [see the Analog-to-Digital Converter and Comparator chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual for more information]:

  1. Register ADCTL2 at address 0x7101, containing the following bits:
    • CLKDIV2EN, a /2 divide enable that scales CPU Clock by 1/2 for use by the ADC
    • ADCNONOVERLAP, a bit enable that removes the conversion/sample overlap timing
  2. Addition of bit field ONESHOT in the existing ADCSOCPRIORITYCTL register. When enabled, the ONESHOT bit field will only let the first SOC complete if multiple SOCs are received at the same time. This is applicable for all SOCs that are in Round-Robin Priority. SOCs in High-Priority mode are not effected by this function.

Workaround(s)

Not applicable