Revision(s) Affected

0, A, B, C, D, E, F and G

Details

The ADC result status flags INT_SEQ1 and INT_SEQ2 bit fields (bits 0 and 1, respectively) in the ADC_ST_FLG register indicate the availability of new ADC results after conversions and initiation of the ADC interrupts.

The update of the ADC result register requires one extra ADC cycle to complete after the status flags INT_SEQ1 and INT_SEQ2 bit(s) are set. The result of reading the result register prior to this extra cycle will result in old data being read (reset value/previous conversion result).

If auto-sequencers are enabled with a non-zero value in the MAXCONV register, the last result register update takes an additional ADC cycle from the time the INT_SEQ1 or INT_SEQ2 flag is set.

Workaround(s)

Delay the read of the ADC result register(s) by at least one ADC clock period. This delay can be implemented by using software delay loops.

If the ADC result register(s) are read using the ADC interrupt, rather than polling, the wait period introduced by the ISR (interrupt service routine) could minimize the delay needed in software. This ISR branching delay is generally greater than 8 SYSCLKOUT cycles.

The ratio of the ADC clock (ADCCLK) to the CPU clock (SYSCLKOUT) determines the size of the software delay. For example, if ADCCLK = 10 MHz, the software delay should be at least 100 ns.

Timing example to estimate the software delay:

1. Get the HSPCLK prescaler value − HISPCP
2. Get the ADCCLK prescaler value − ADCCLKPS
3. Get the CPS (ADCCTRL1[7]) value − CPS
4. Software wait-period in CPU cycles (SYSCLKOUT) before the ADC result register read is defined as:

   
   Software wait = (HISPCP *2) * (ADCCLKPS * 2) * (CPS +1) cycles
   If HISPCP or ADCCLKPS is 0, then the respective terms should be (HISPCP +1)
   or (ADCCLKPS+1)