SPRZ193T January   2003  – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

 

  1.   1
  2. 1Introduction
  3. 2Device and Development Tool Support Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
  6. 5Known Design Exceptions to Functional Specifications
    1.     Advisory
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    28.     Advisory
    29.     Advisory
    30.     Advisory
    31.     Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

Advisory

ADC: Device Has Higher Gain Error Than the Design Goal of 1% FSR on All of the B0−B7 Channels

Revision(s) Affected

0 and A

Details

The device has a higher gain error than the design goal of 1% FSR on all of the B0−B7 channels. The gain error varies across channels A0−A7 and B0−B7.

Based on the current data obtained on B group channels, all B group channels show a uniform gain error as high as 2 to 3%.

Workaround(s)

The channel-to-channel gain error data across channels are listed in Table 5-4. This should help in calibrating in software or hardware. This was fixed in Revision B silicon.

Table 5-4 Channel-to-Channel Offset Error Data Across Channels (176-Pin PGF)
ADC CHANNELSA0A1A2A3A4A5A6A7B0B1B2B3B4B5B6B7
Gain Error in %0.200.180.520.530.530.550.540.542.922.922.922.932.932.932.932.97
Offset in LSB Counts14.8015.644.869.825.82–14.57–13.98–31.7820.9421.9822.4823.3922.3923.1423.6424.91
Note:

The data provided are typical values only. These values are obtained from bench characterization at room temperature on a few devices.

TMX samples are not fully screened for all ADC parameters. If there are devices that have worse performance than suggested issues/values, it is recommended that the part be replaced.