SPRZ193T January   2003  – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

 

  1.   1
  2. 1Introduction
  3. 2Device and Development Tool Support Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
  6. 5Known Design Exceptions to Functional Specifications
    1.     Advisory
    2.     Advisory
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    4.     Advisory
    5.     Advisory
    6.     Advisory
    7.     Advisory
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    10.     Advisory
    11.     Advisory
    12.     Advisory
    13.     Advisory
    14.     Advisory
    15.     Advisory
    16.     Advisory
    17.     Advisory
    18.     Advisory
    19.     Advisory
    20.     Advisory
    21.     Advisory
    22.     Advisory
    23.     Advisory
    24.     Advisory
    25.     Advisory
    26.     Advisory
    27.     Advisory
    28.     Advisory
    29.     Advisory
    30.     Advisory
    31.     Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

Advisory

QEP: QEP Inputs in GPIO Asynchronous Mode

Revision(s) Affected

0, A, B, C, D, E, F and G

Details

If any of the QEP input pins are configured for GPIO asynchronous input mode via the GPxQSELn registers, the QEP module may not operate properly. For example, QPOSCNT may not reset or latch properly, and pulses on the input pins may be missed. This is because the QEP peripheral assumes the presence of external synchronization to SYSCLKOUT on inputs to the module.

For proper operation of the QEP module, input GPIO pins should be configured via the GPxQSELn registers for synchronous input mode (with or without qualification). This is the default state of the GPxQSEL registers at reset. All existing QEP peripheral examples supplied by TI also configure the GPIO inputs for synchronous input mode.

The asynchronous mode should not be used for QEP module input pins.

Workaround(s)

Configure GPIO inputs configured as QEP pins for non-asynchronous mode (any GPxQSELn register option except “11b = Asynchronous”).