SPRZ193T January   2003  – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

 

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  2. 1Introduction
  3. 2Device and Development Tool Support Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
  6. 5Known Design Exceptions to Functional Specifications
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  7. 6Documentation Support
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Advisory

XINTF: XBANK Does Not Properly Extend an Access

Revision(s) Affected

0, A, B, C, D, E, F and G

Details

When XTIMCLK is not equal to SYSCLKOUT, the XBANK logic may not properly delay a pending access. This occurs for some combinations of XINTF zone wait states and XBANK delay cycles. There are two cases when this occurs.

Case 1: When XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = XTIMCLK

A pending access may not be delayed by the XBANK logic if either:

  • WLEAD + WACTIVE + WTRAIL <= XBANK[BCYC] or
  • RLEAD + RACTIVE + RTRAIL <= XBANK[BCYC]

Where WLEAD, WACTIVE, WTRAIL, RLEAD, RACTIVE, RTRAIL are defined as shown in Table 5-2.

Table 5-2 Pending Access Relationships
X2TIMING = 0X2TIMING = 1
WLEADXTIMING x [XWRLEAD]XTIMING x [XWRLEAD] x 2
WACTIVEXTIMING x [XWRACTIVE] + 1XTIMING x [XWRACTIVE] x 2 + 1
WTRAILXTIMING x [XWRTRAIL]XTIMING x [XWRTRAIL] x 2
RLEADXTIMING x [XRDLEAD]XTIMING x [XRDLEAD] x 2
RACTIVEXTIMING x [XRDACTIVE] + 1XTIMING x [XRDACTIVE] x 2 + 1
RTRAILXTIMING x [XRDTRAIL]XTIMING x [XRDTRAIL] x 2

In Table 5-2, XTIMINGx refers to the XTIMING register for Zone x. When XBANK delay cycles are added between two accesses, Zone x refers to the first zone in the sequence. For example: if XBANK[BANK] = 7, then delay cycles will be added to any access into or out of Zone 7. This means:

  • Access to Zone 0 followed by Zone 7: the timing of Zone 0 is critical.
  • Access to Zone 1 followed by Zone 7: the timing of Zone 1 is critical.
  • Access to Zone 7 followed by Zone 0: the timing of Zone 7 is critical.

Thus, the timing of any zone involved in bank switching must be considered.

Case 2) When XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = 1/2 XTIMCLK:

A pending access may not be delayed properly by the XBANK logic if XBANK[BCYC] = 4 or XBANK[BCYC] = 6.

Workaround(s)

Case 1) If XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = XTIMCLK, then select:

  • XBANK[BCYC] <= WLEAD + WACTIVE + WTRAIL and
  • XBANK[BCYC] <= RLEAD + RACTIVE + RTRAIL

When XBANK delay cycles are added between two accesses, the timing restriction applies to the first zone accessed as described earlier. The timing of any zone involved in bank switching must be considered.

Table 5-3 shows examples of valid XBANK[BCYC] selections. This list is not exhaustive.

Table 5-3 Examples of Valid XBANK Selections
XWRLEAD
XRDLEAD		WRACTIVE
XRDACTIVE		XWRTRAIL
XRDTRAIL		X2TIMINGWLEAD +
WACTIVE +
WTRAIL		Choose
XBANK[BCYC]
12105< 5
13106< 6
23107< 7
10113< 3
11015< 5
11117< 7

Case 2: If XTIMCLK = 1/2 SYSCLKOUT and XCLKOUT = 1/2 XTIMCLK, then select:

  • XBANK[BCYC] != 4 and
  • XBANK[BCYC] != 6